Integrated circuit device with source/drain barrier
Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.
1. A method comprising:
receiving a workpiece that includes:
a substrate; and
a device fin extending above the substrate, wherein the device fin includes a channel region;
etching a portion of the device fin adjacent the channel region, wherein the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess;
cleaning the workpiece to remove a first portion of the dielectric barrier from the source/drain recess such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess; and
forming a source/drain feature within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.
2. The method of claim 1 , wherein the cleaning of the workpiece includes a dry cleaning process configured to remove a side portion of the dielectric barrier disposed along a side surface of the source/drain recess and to leave the bottommost portion of the dielectric barrier.
3. The method of claim 2 , wherein the cleaning of the workpiece further includes a wet cleaning process configured such that the dielectric barrier remains after the wet cleaning process.
4. The method of claim 2 , wherein the dry cleaning process removes the side portion of the dielectric barrier such that a side surface of the source/drain feature is free of the dielectric barrier and physically contacts the channel region.
5. The method of claim 1 , wherein:
the received workpiece further includes a gate stack disposed on and around the channel region; and
the etching of the portion of the device fin is performed to a depth such that a bottommost surface of the dielectric barrier extends to a depth below a bottommost surface of the gate stack.
6. The method of claim 5 , wherein a topmost surface of the dielectric barrier is disposed above the bottommost surface of the gate stack.
7. The method of claim 1 , wherein:
the received workpiece further includes a gate stack disposed on and around the channel region; and
the etching of the portion of the device fin is performed to a depth such that a bottommost surface of the dielectric barrier extends to a depth substantially coplanar with a bottommost surface of the gate stack.
8. The method of claim 1 , wherein:
the received workpiece further includes a gate stack disposed on and around the channel region; and
the etching of the portion of the device fin is performed to a depth such that a bottommost surface of the dielectric barrier extends to a depth above a bottommost surface of the gate stack.
9. The method of claim 1 , wherein:
the received workpiece further includes an isolation feature disposed alongside the device fin; and
the etching of the portion of the device fin is performed to a depth such that the dielectric barrier extends below a topmost surface of the isolation feature.
10. The method of claim 1 , wherein:
the device fin is disposed between and extends above a first isolation feature and a second isolation feature; and
the dielectric barrier extends from the first isolation feature to the second isolation feature.
11. A method comprising:
receiving a substrate and a fin formed on the substrate that includes a channel region;
etching the fin to define a first source/drain recess on a first side of the channel region and a second source/drain recess on a second side of the channel region opposite the first side;
forming a first insulating barrier within a bottommost portion of the first source/drain recess and a second insulating barrier within a bottommost portion of the second source/drain recess; and
epitaxially growing a first source/drain feature within the first source/drain recess on the first insulating barrier and a second source/drain feature within the second source/drain recess on the second insulating barrier.
12. The method of claim 11 , wherein the first insulating barrier and the second insulating barrier are physically separated by the channel region.
13. The method of claim 11 , wherein the first insulating barrier and the second insulating barrier do not extend underneath the channel region.
14. The method of claim 11 , wherein the first insulating barrier and the second insulating barrier are formed by the etching of the fin to define the first source/drain recess and the second source/drain recess.
15. The method of claim 11 further comprising cleaning the first source/drain recess and the second source/drain recess after the etching of the fin and prior to the epitaxially growing of the first source/drain feature and the second source/drain feature, wherein the cleaning is configured to leave the first insulating barrier within the bottommost portion of the first source/drain recess and the second insulating barrier within the bottommost portion of the second source/drain recess.
16. The method of claim 15 , wherein the cleaning is configured to remove a first portion of the first insulating barrier along a side surface of the first source/drain recess and to leave a second portion of the first insulating barrier along a bottommost surface of the first source/drain recess.
17. A device comprising:
a substrate; and
a device fin disposed on the substrate, wherein the device fin includes:
a channel region;
a source/drain feature adjacent the channel region; and
a dielectric barrier disposed between a bottommost portion of the source/drain feature and the substrate, wherein a side surface of the source/drain feature is free of the dielectric barrier and physically contacts the channel region.
18. The device of claim 17 further comprising a gate stack disposed overwrapping the channel region of the device fin such that a bottommost surface of the gate stack is disposed below a topmost surface of the device fin, wherein the dielectric barrier extends below the bottommost surface of the gate stack.
19. The device of claim 17 , wherein the dielectric barrier does not extend underneath the channel region.
20. The device of claim 17 , wherein the dielectric barrier has a top surface that is curvilinear and convex.