Systems and methods for single-molecule nucleic-acid assay platforms
Integrated circuits for a single-molecule nucleic-acid assay platform, and methods for making such circuits are disclosed. In one example, a method includes transferring one or more carbon nanotubes to a complementary metal-oxide semiconductor (CMOS) substrate, and forming a pair of post-processed electrodes on the substrate proximate opposing ends of the one or more carbon nanotubes.
1. A method of making an integrated circuit for a single-molecule nucleic-acid assay platform, comprising:
transferring one or more carbon nanotubes to a complementary metal-oxide semiconductor (CMOS) integrated circuit; and
forming a pair of post-processed electrodes proximate opposing ends of the one or more carbon nanotubes, the post-processed electrodes electrically connecting the one or more carbon nanotubes to the CMOS integrated circuit.
2. The method of claim 1 , wherein transferring the one or more carbon nanotubes comprises spinning the one or more carbon nanotubes from a suspension to the CMOS integrated circuit.
3. The method of claim 1 , wherein transferring the one or more carbon nanotubes comprises:
forming the one or more carbon nanotubes on a transfer substrate;
applying a layer of polymer to the transfer substrate to adhere the one or more carbon nanotubes to the layer of polymer; and
placing the layer of polymer with the one or more carbon nanotubes on the CMOS integrated circuit.
4. The method of claim 1 , wherein transferring the one or more carbon nanotubes comprises:
placing the one or more carbon nanotubes in a suspension proximate a pair of preformed electrodes on the substrate; and
applying a voltage across the pair of preformed electrodes, whereby a force is applied to the one or more carbon nanotubes to urge the carbon nanotubes to be disposed across the pair of preformed electrodes.
5. The method of claim 1 , wherein the CMOS integrated circuit comprises surface-exposed electrodes, and forming the pair of post-processed electrodes comprises depositing titanium on a pair of the surface-exposed electrodes.
6. The method of claim 1 , wherein the CMOS integrated circuit comprises surface-exposed electrodes, and forming the pair of post-processed electrodes comprises etching away a pair of surface-exposed electrodes and replacing the pair of surface-exposed electrodes with a pair of titanium electrodes.
7. The method of claim 1 , further comprising forming one or more reference electrodes on the CMOS integrated circuit to allow control of an electrolytic gating potential.
8. The method of claim 7 , wherein the CMOS integrated circuit comprises one or more surface-exposed electrodes, and forming the one or more reference electrodes comprises etching away the surface-exposed electrodes.
9. The method of claim 8 , wherein the one or more surface-exposed electrodes comprises aluminum, and forming the one or more reference electrodes further comprises replacing the surface-exposed electrodes with gold electrodes.
10. The method of claim 9 , wherein forming the one or more reference electrodes further comprises electroplating silver on the gold electrodes.
11. The method of claim 10 , wherein forming the one or more reference electrodes further comprises exposing the electroplated electrodes to FeCl 3 to form Ag/AgCl electrodes.
12. The method of claim 7 , wherein the CMOS integrated circuit comprises one or more surface-exposed electrodes, and forming the one or more reference electrodes comprises depositing platinum on the one or more surface-exposed electrodes.
13. The method of claim 8 , wherein forming the one or more reference electrodes further comprises replacing the surface-exposed electrodes with one or more platinum electrodes.
14. The method of claim 1 , further comprising forming a point defect on a portion of the one or more carbon nanotubes.
15. The method of claim 1 , further comprising coupling the one or more post-processed electrodes to a ball-grid array (BGA) package.
16. The method of claim 15 , wherein the coupling comprises wire bonding.
17. The method of claim 16 , wherein wirebonds are exposed on a surface of the CMOS integrated circuit, the method further comprising covering the exposed wirebonds using dam-and-fill material.
18. The method of claim 1 , wherein the pair of post-processed electrodes is formed after the one or more carbon nanotubes are transferred.
19. The method of claim 1 , wherein the semiconductor integrated circuit includes a multilevel wiring structure, the multilevel wiring structure disposed between the one or more carbon nanotubes and a substrate of the CMOS integrated circuit.
20. The method of claim 1 , further comprising immobilizing a capture probe directly on each of the one or more carbon nanotubes.