IP Library › Granted Patent US 10,163,623
Granted Patent B1
US 10,163,623 · App. 15/799,489 · Granted Dec 25, 2018

Etch method with surface modification treatment for forming semiconductor structure

Inventors: Andrew Joseph Kelly (Hsinchu County, TW); Yi-Hsiu Chen (Taipei, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L21/0217H01L21/02123H01L21/02129H01L21/02164H01L21/02236H01L21/02343H01L21/02359H01L21/02524H01L21/02532H01L21/31111H01L21/76224H01L21/823821H01L29/66545H01L29/66795
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Quick Facts
Patent No.
US 10,163,623
App. No.
15/799,489
Granted
Dec 25, 2018
Kind
B1
Abstract

An etching method with a surface modification treatment for forming a semiconductor structure is provided. The method includes providing a semiconductor substrate, forming a silicon nitride (SiN) layer on the semiconductor substrate, and forming a silicon-containing layer on the semiconductor substrate and beside the SiN layer. The silicon-containing layer includes a silicon dioxide layer, a n-type silicon-containing layer, a p-type silicon-containing layer or a combination thereof. The method further includes performing a surface modification treatment onto the SiN layer and the silicon-containing layer by using a surface modification solution, thereby forming a modified layer on the SiN layer and the silicon-containing layer. The method further includes removing a portion of the modified layer and its underlying SiN layer by a wet etching operation, while the other portion of the modified layer and its underlying silicon-containing layer remain, and removing the other portion of the modified layer.

Claims (65)

1. An etching method with a surface modification treatment for forming a semiconductor structure, comprising:

providing a semiconductor substrate;

forming a silicon nitride (SiN) layer on the semiconductor substrate;

forming a silicon-containing layer on the semiconductor substrate and beside the SiN layer, wherein the silicon-containing layer comprises a silicon dioxide layer, a n-type silicon-containing layer, a p-type silicon-containing layer or a combination thereof;

removing a first portion of the SiN layer by a first wet etching operation, thereby exposing a second portion of the SiN layer while the silicon-containing layer remains;

performing at least one etching cycle to the second portion of the SiN layer and the silicon-containing layer, the at least one etching cycle comprising:

performing a surface modification treatment onto the second portion of the SiN layer and the silicon-containing layer by using a surface modification solution, thereby forming a modified layer on the second portion of the SiN layer and the silicon-containing layer; and

removing a portion of the modified layer and its underlying second portion of the SiN layer by a second wet etching operation, while the other portion of the modified layer and its underlying silicon-containing layer remain; and

removing the other portion of the modified layer.

2. The method of claim 1 , wherein forming the SiN layer on the semiconductor substrate further comprises:

forming a fin structure on the semiconductor substrate;

forming a dummy gate structure on the fin structure, wherein the dummy gate structure is substantially orthogonal to the fin structure;

forming a plurality of trenches in the fin structure on two opposite sides of the dummy gate structure;

conformally depositing a buffer oxide layer in the trenches; and

forming the SiN layer to fill the trenches and on the buffer oxide layer.

3. The method of claim 2 , wherein forming the silicon-containing layer on the semiconductor substrate and beside the SiN layer further comprises:

replacing the dummy gate structure by a metal gate structure, wherein the metal gate structure comprises:

a metal gate layer; and

a high-k layer surrounding the metal gate layer; and

forming the silicon-containing layer over the metal gate layer and the high-k layer.

4. The method of claim 1 , wherein forming the SiN layer on the semiconductor substrate further comprises:

forming a fin structure on a semiconductor substrate, wherein the fin structure comprises a first fin and a second fin, wherein the first fin comprises a n type material or a p type material, and the second fin comprises a material opposite to the first fin;

forming dummy gate structures respectively on the first fin and the second fin;

forming a spacer layer on sidewalls of the dummy gate structures;

recessing the first fin and the second fin on two respective sides of the corresponding dummy gate structures, thereby forming a plurality of first recesses in the first fin and a plurality of second recesses in the second fin; and

forming the SiN layer on one of each of the first recesses or each of the second recesses.

5. The method of claim 4 , wherein forming the silicon-containing layer on the semiconductor substrate and beside the SiN layer further comprises:

forming the silicon-containing layer in the exposed first or second recesses, wherein the silicon-containing layer is the n-type silicon-containing layer, the p-type silicon-containing layer.

6. The method of claim 1 , wherein forming the SiN layer on the semiconductor substrate further comprises:

forming a fin structure on the semiconductor substrate;

forming a dummy gate structure on the fin structure, wherein the dummy gate structure is substantially orthogonal to the fin structure;

forming the SiN layer conformal to sidewalls of the dummy gate structure;

forming a first spacer layer conformal to and covering the SiN layer;

recessing the fin structure on two opposite sides of the dummy gate structure, thereby forming a plurality of trenches; and

forming a source/drain region and an oxide layer in each of the trenches, wherein the oxide layer is formed over the source/drain region, and wherein forming the silicon-containing layer on the semiconductor substrate and beside the SiN layer further comprises:

replacing a dummy gate structure by a metal gate structure, wherein the metal gate structure comprises:

a metal gate layer; and

a high-k layer surrounding the metal gate layer; and

forming the silicon-containing layer over the metal gate layer and the high-k layer.

7. The method of claim 1 , before removing the portion of the modified layer and its underlying second portion of the SiN layer of one or more etching cycles, the method further comprises:

performing a first oxidation operation on the silicon-containing layer, thereby forming a first oxidized layer on the silicon-containing layer, wherein the silicon-containing layer comprises the n-type silicon-containing layer or the p-type silicon-containing layer.

8. The method of claim 7 , wherein the first oxidation operation is performed by applying an oxidizing solution to the silicon-containing layer.

9. The method of claim 8 , wherein the oxidizing solution comprises aqueous ozone, hydrogen peroxide, a mixture of hydrogen peroxide and ammonium hydroxide, a mixture of sulfuric acid and hydrogen peroxide, or a mixture of hydrochloric acid and hydrogen peroxide.

10. The method of claim 1 , wherein the first wet etching operation and the second wet etching operation are performed by applying phosphoric acid-containing solution.

11. The method of claim 1 , wherein removing the other portion of the modified layer further comprises performing a second oxidation operation on the modified layer to form a second oxidized layer.

12. The method of claim 11 , wherein removing the other portion of the modified layer further comprises removing the second oxidized layer by a pre-clean process.

13. The method of claim 1 , after the at least one etching cycle and before removing the other portion of the modified layer, the method further comprises:

performing another surface modification treatment to form a modified layer to cover a top surface of the semiconductor structure.

14. The method of claim 1 , wherein the surface modification solution comprises N,N-(dimethylamino)trimethylsilane.

15. The method of claim 1 , wherein removing the other portion of the modified layer comprises directly performing a diluted hydrogen fluoride (DHF) cleaning operation on the modified layer.

16. A method of forming a semiconductor device, the method comprising:

providing a semiconductor substrate on which a silicon nitride layer and a silicon-containing layer are formed;

performing at least one etching cycle to the SiN layer and the silicon-containing layer, the at least one etching cycle comprising:

reacting a top surface of the SiN layer and a top surface of the silicon-containing layer with a surface modification solution, thereby modifying the top surface of the SiN layer and the top surface of the silicon-containing layer; and

removing at least a portion of the SiN layer by a wet etching operation, while the silicon-containing layer remains; and

removing the top surface of the silicon-containing layer.

17. The method of claim 16 , further comprising performing the wet etching operation on the SiN layer and the silicon-containing layer prior to the at least one etching cycle.

18. The method of claim 16 , wherein the at least one etching cycle is performed under a temperature of substantially 120° C.−170° C.

19. A method of forming a semiconductor device, the method comprising:

providing a semiconductor substrate on which a silicon nitride (SiN) layer and a silicon-containing layer are formed;

performing at least one etching cycle to the SiN layer and the silicon-containing layer until a predetermined thickness of the SiN layer is achieved, the at least one etching cycle comprising:

applying a silane compound on the SiN layer and the silicon-containing layer, thereby forming a modified layer on the SiN layer and a modified layer on the silicon-containing layer; and

performing a wet etching operation on the modified layer of the SiN layer and the modified layer of the silicon-containing layer, wherein the wet etching operation has an etching selectivity to the modified layer on the SiN layer with respect to the modified layer on the silicon-containing layer; and

removing the modified layer on the silicon-containing layer.

20. The method of claim 19 , further comprising performing the wet etching operation on the SiN layer and the silicon-containing layer prior to the at least one etching cycle.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2017
From: KELLY, ANDREW JOSEPH; CHEN, YI-HSIU
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 044012/0430 →
Cited By (2)
US 12,203,021 US 12,615,983