IP Library Granted Patent US 10,497,577
Granted Patent B2
US 10,497,577 · App. 15/801,194 · Granted Dec 3, 2019

Fin field-effect transistor device and method

Inventors: Yin Wang (New Taipei, TW); Hung-Ju Chou (Taipei, TW); Jiun-Ming Kuo (Taipei, TW); Wei-Ken Lin (Tainan, TW); Chun Te Li (Renwu Township, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L21/3105H01L21/31051H01L21/823821H01L21/823878H01L29/0649H01L29/7851H01L29/7853H01L21/31053
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Quick Facts
Patent No.
US 10,497,577
App. No.
15/801,194
Granted
Dec 3, 2019
Kind
B2
Abstract

A method includes forming a semiconductor capping layer over a first fin in a first region of a substrate, forming a dielectric layer over the semiconductor capping layer, and forming an insulation material over the dielectric layer, an upper surface of the insulation material extending further away from the substrate than an upper surface of the first fin. The method further includes recessing the insulation material to expose a top portion of the first fin, and forming a gate structure over the top portion of the first fin.

Claims (53)

1. A method comprising:

forming a semiconductor capping layer over a first fin in a first region of a substrate, wherein forming the semiconductor capping layer comprises forming a silicon capping layer over the first fin;

forming a dielectric layer over the semiconductor capping layer;

forming an insulation material over the dielectric layer, an upper surface of the insulation material extending further away from the substrate than an upper surface of the first fin;

recessing the insulation material to expose a top portion of the first fin; and

forming a gate structure over the top portion of the first fin.

2. The method of claim 1 , further comprising, before forming the semiconductor capping layer:

replacing a first portion of the substrate in the first region with an epitaxial semiconductor material; and

patterning the epitaxial semiconductor material to form the first fin.

3. The method of claim 1 , further comprising treating the semiconductor capping layer with a nitride-containing gas before forming the dielectric layer over the semiconductor capping layer.

4. The method of claim 1 , wherein the first fin and the substrate comprise a same material.

5. The method of claim 1 , further comprising curing the insulation material before recessing the insulation material.

6. The method of claim 5 , wherein the semiconductor capping layer is a silicon capping layer, and the dielectric layer is a silicon nitride layer, wherein curing the insulation material converts a top layer of the dielectric layer into silicon oxynitride.

7. The method of claim 5 , wherein the curing comprises:

performing a first anneal process;

performing a planarization process after the first anneal process; and

performing a second anneal process.

8. The method of claim 7 , wherein the planarization process removes top portions of the insulation material and exposes a mask layer over the upper surface of the first fin.

9. The method of claim 7 , wherein performing the first anneal process comprises:

performing a first wet steam anneal; and

performing a first dry anneal after the first wet steam anneal.

10. The method of claim 9 , wherein the first dry anneal is performed in an ambient comprising nitrogen.

11. The method of claim 9 , wherein performing the second anneal process comprises:

performing a second wet steam anneal; and

performing a second dry anneal after the second wet steam anneal.

12. The method of claim 1 , wherein the first region is a PMOS region, wherein the method further comprises forming a second fin in an NMOS region of the substrate that is adjacent to the PMOS region, wherein the semiconductor capping layer and the dielectric layer are formed over the first fin and over the second fin.

13. The method of claim 1 , wherein recessing the insulation material removes the semiconductor capping layer and the dielectric layer disposed over sidewalls of the top portion of the first fin.

14. A method of forming Fin Field-Effect Transistor (FinFET) device, the method comprising:

forming a first fin in a PMOS region of a substrate;

forming a second fin in an NMOS region of the substrate adjacent to the PMOS region;

forming a silicon capping layer over the first fin and the second fin;

performing a nitridation treatment on the silicon capping layer;

forming a first dielectric material over the silicon capping layer;

depositing a second dielectric material between and over the first fin and the second fin, wherein the first dielectric material is between the silicon capping layer and the second dielectric material;

performing a thermal process to cure the second dielectric material;

recessing the second dielectric material after the thermal process to expose a top portion of the first fin and a top portion of the second fin; and

forming a first gate structure over the first fin and a second gate structure over the second fin.

15. The method of claim 14 , wherein forming the silicon capping layer comprises forming the silicon capping layer conformally over the first fin and the second fin.

16. The method of claim 14 , wherein performing the nitridation treatment comprises treating the silicon capping layer with a gas comprising ammonia.

17. The method of claim 14 , wherein forming the first dielectric material comprises conformally forming a layer of silicon nitride over the silicon capping layer, wherein performing the thermal process converts a top layer of the first dielectric material into silicon oxynitride.

18. A method of forming a Fin Field-Effect Transistor (FinFET) device, the method comprising:

forming a fin protruding above a substrate;

forming a silicon capping layer over the fin;

treating the silicon capping layer with a nitridation process;

forming a first dielectric layer over the treated silicon capping layer;

forming an insulation material over the substrate and around the fin, the insulation material covering the first dielectric layer;

performing a first curing process to cure at least portions of the insulation material;

removing top portions of the insulation material to expose the first dielectric layer; and

performing a second curing process to cure bottom portions of the insulation material after removing top portions of the insulation material.

19. The method of claim 18 , further comprising:

recessing the bottom portions of the insulation material below an upper surface of the fin distal the substrate; and

forming a gate structure over the fin.

20. The method of claim 18 , wherein the second curing process converts a top layer of the first dielectric layer into an oxide of a material of the first dielectric layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 6, 2018
From: WANG, YIN; CHOU, HUNG-JU; KUO, JIUN-MING; LIN, WEI-KEN; LI, CHUN TE
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 044845/0868 →
Continuity (2)
Provisional Application 62552986 · Aug 31, 2017
Related Publication 20190067027A1 · Feb 28, 2019
Cited By (3)
US 12,400,910 US 12,419,100 US 12,490,454