Method of manufacturing semiconductor devices and semiconductor devices
In a method of manufacturing a semiconductor device including a Fin FET, a fin structure, which has an upper fin structure made of SiGe and a bottom fin structure made of a different material than the upper fin structure, is formed, a cover layer is formed over the fin structure, a thermal operation is performed on the fin structure covered by the cover layer, and a source/drain epitaxial layer is formed in a source/drain region of the upper fin structure. The thermal operation changes a germanium distribution in the upper fin structure.
1 . A semiconductor device, comprising:
a recrystallized fin disposed on a substrate extending in a first direction;
a conductive layer crossing over a first region of the fin and extending in a second direction;
a high-k dielectric layer extending in the second direction disposed between the conductive layer and fin; and
an epitaxial layer disposed over a second region of the fin on opposing sides of the conductive layer,
wherein the first region of the fin includes SiGe having a Ge concentration that has a peak in a range from 30 atomic % to 40 atomic % at a depth from a surface of fin and decreases from the depth toward a center of the first region, and wherein the Ge concentration at the surface of the first region ranges from 5 atomic % to 15 atomic %.
2 . The semiconductor device of claim 1 , wherein the depth from the surface of the first region ranges from 1 nm to 5 nm.
3 . The semiconductor device of claim 2 , wherein a lowest Ge concentration in the first region ranges from 10 atomic % to 25 atomic %.
4 . The semiconductor device of claim 2 , wherein a difference between a highest Ge concentration and a lowest Ge concentration in the first region ranges from 5% to 35%.
5 . The semiconductor device of claim 4 , wherein:
the fin includes a fin bottom portion and a fin upper portion including the first region, and
the fin bottom portion is made of a different semiconductor material than the fin upper portion.
6 . The semiconductor device of claim 5 , further comprising a liner layer disposed on side faces of the fin bottom portion.
7 . The semiconductor device of claim 6 , wherein the liner layer covers a bottom portion of the fin upper portion.
8 . The semiconductor device of claim 4 , wherein a width of the first portion along the second direction at a level of an upper surface of an isolation insulating layer is in a range from 15 nm to 30 nm.
9 . The semiconductor device of claim 1 , wherein the Ge concentration has two peaks.
10 . The semiconductor device of claim 1 , wherein the Ge concentration at a center of the fin is in a range of 15 atomic % to 20 atomic %.
11 . A semiconductor device, comprising:
a recrystallized fin having a first region and a second region on opposing sides of the first region;
a capping layer disposed over the first region;
a gate structure including a high-k dielectric layer disposed over the capping layer and a gate electrode layer disposed over the high-k dielectric layer;
an epitaxial layer formed in the second region,
wherein the first region includes a SiGe layer having a Ge concentration having a peak at a depth from a surface of the capping layer that decreases from the depth toward a center of the first region, and wherein the Ge concentration at a surface of the first region ranges from 5 atomic % to 15 atomic % and a peak Ge concentration in a range of 30 atomic % to 40 atomic %.
12 . The semiconductor device of claim 11 , wherein the depth from the surface of the first region is in a range from 1 nm to 5 nm.
13 . The semiconductor device of claim 11 , wherein the Ge concentration at the peak is higher than a Ge concentration in the capping layer.
14 . The semiconductor device of claim 11 , wherein a difference between a highest Ge concentration and a lowest Ge concentration in the first region ranges from 5% to 35%.
15 . The semiconductor device of claim 11 , wherein the Ge concentration has two peaks.
16 . A semiconductor device, comprising:
a channel region including a recrystallized fin having a fin bottom structure and a fin upper structure including a first region and a second region;
an isolation insulating layer from which the first region protrudes;
a capping layer disposed over the first region;
a gate structure including a high-k dielectric layer disposed over the capping layer and a conductive layer disposed over the high-k dielectric layer; and
a source/drain epitaxial layer formed in the source/drain region,
wherein the channel region includes a SiGe layer having a Ge concentration that has a peak at a depth from a surface of the capping layer and gradually and continuously decreases from the depth to a center of the first region, and wherein the Ge concentration at the surface of the capping layer ranges from 5 atomic % to 15 atomic %, and a peak Ge concentration in a range of 30 atomic % to 40 atomic %.
17 . The semiconductor device of claim 16 , the depth from the surface of the capping layer is in a range from 1 nm to 5 nm.
18 . The semiconductor device of claim 17 , wherein a lowest Ge concentration in the channel region ranges from 10 atomic % to 25 atomic %.
19 . The semiconductor device of claim 16 , wherein a difference between a highest Ge concentration and a lowest Ge concentration in the first region ranges from 5% to 35%.
20 . The semiconductor device of claim 16 , wherein the Ge concentration has two peaks along a width of the fin.