Method of manufacturing semiconductor device on hybrid substrate

1. A method, comprising:

bonding a first semiconductor substrate onto a second semiconductor substrate with an isolator layer between the first semiconductor substrate and the second semiconductor substrate;

etching a first portion of the first semiconductor substrate and a first portion of the isolator layer until the second semiconductor substrate is exposed, wherein a second portion of the first semiconductor substrate and a second portion of the isolator layer remain over the second semiconductor substrate;

epitaxially growing an epitaxy layer over the exposed second semiconductor substrate;

etching the second portion of the first semiconductor substrate to form an upper portion of a first fin, etching the second portion of the isolator layer, etching the second semiconductor substrate to form a lower portion of the first fin, etching the epitaxy layer to form an upper portion of a second fin and etching the second semiconductor substrate to form a lower portion of the second fin under the upper portion of the second fin;

forming a first silicon liner layer over the first fin, the second fin and the second semiconductor substrate;

forming a nitride liner layer over the first silicon liner layer;

forming an isolation filler over the nitride liner layer; and

recessing the isolation filler, the first silicon liner layer, and the nitride liner layer such that the upper portion of the second fin has a first portion protruding from the recessed isolation filler, the first silicon liner layer, and the nitride liner layer and a second portion buried under the recessed isolation filler, the first silicon liner layer, and the nitride liner layer, wherein a top of the recessed isolation filler is higher than an interface between the upper portion and the lower portion of the second fin.

2. The method of claim 1 , wherein recessing the first silicon liner layer is performed such that a width of the first portion of the upper portion of the second fin is smaller than a width of the second portion of the upper portion of the second fin.

3. The method of claim 1 , further comprising:

forming a second silicon liner layer over the first portion of the upper portion of the second fin after recessing the first silicon liner layer.

4. The method of claim 3 , wherein forming the second silicon liner layer is performed such that the first silicon liner layer and the second silicon liner layer have different thicknesses.

5. The method of claim 3 , wherein the first silicon liner layer and the second silicon liner layer comprises the same semiconductor material.

6. The method of claim 3 , wherein forming the second silicon liner layer is performed such that the second silicon liner layer is formed over the recessed isolation filler.

7. The method of claim 1 , further comprising:

before epitaxially growing the epitaxy layer over the second semiconductor substrate, bonding the second semiconductor substrate onto the first semiconductor substrate having a top surface with a ( 110 ) crystal orientation with the isolator layer between the second semiconductor substrate and the first seimiconductor substrate.

8. A method, comprising:

bonding a first semiconductor substrate having a top surface with a crystal orientation onto a second semiconductor substrate having a top surface with a crystal orientation with an insulator layer between the first semiconductor substrate and the second semiconductor substrate;

etching the first semiconductor substrate to form an upper fin, etching the insulator layer, and etching the second semiconductor substrate to form a lower fin under the upper fin, wherein the etched insulator layer is interposed between the upper fin and the lower fin;

forming an isolation filler over the upper fin, the etched insulator layer, and the lower fin;

recessing the isolation filler such that a top of the recessed isolation filler is higher than an interface between the etched insulator layer and the lower fin;

forming a gate structure across the upper fin;

etching the recessed isolation filler and the insulator layer to suspend a portion of the upper fin that is not covered by the gate structure; and

forming an epitaxy layer around the suspended portion of the upper fin.

9. The method of claim 8 , further comprising:

forming a first capping liner over the upper fin, the etched insulator layer, and the lower fin prior to forming the isolation filler.

10. The method of claim 9 , further comprising:

removing a first portion of the first capping liner over the top of the recessed isolation filler, wherein a second portion of the first capping liner under the top of the recessed isolation filler remains.

11. The method of claim 10 , further comprising:

forming a second capping liner over the upper fin after removing the first portion of the first capping liner.

12. The method of claim 11 , wherein forming the second capping liner is performed such that a thickness of the first capping liner is greater than a thickness of the second capping liner.

13. A method, comprising:

bonding a first semiconductor substrate onto a second semiconductor substrate with an isolator layer between the first semiconductor substrate and the second semiconductor substrate;

etching a first portion of the first semiconductor substrate and a first portion of the isolator layer until the second semiconductor substrate is exposed, wherein a second portion of the first semiconductor substrate and a second portion of the isolator layer remain over the second semiconductor substrate;

epitaxially growing an epitaxy layer over the exposed second semiconductor substrate;

etching the second portion of the first semiconductor substrate to form an upper portion of a first fin, etching the second portion of the isolator layer, etching the second semiconductor substrate to form a lower portion of the first fin, etching the epitaxy layer to form an upper portion of a second fin, and etching the second semiconductor substrate to form a lower portion of the second fin;

forming a capping liner over the first fin and the second fin;

forming an isolation filler over the capping liner; and

recessing the isolation filler such that a top of the recessed isolation filler is higher than an interface between the upper portion and the lower portion of the second fin.

14. The method of claim 13 , further comprising:

removing a first portion of the capping liner over the top of the recessed isolation filler, wherein the remaining capping liner has a second portion interposed between the upper portion of the second fin and the recessed isolation filler.

15. The method of claim 13 , further comprising:

forming a spacer over a sidewall of the second portion of the first semiconductor substrate and a sidewall of the second portion the isolator layer prior to epitaxially growing the epitaxy layer.

16. The method of claim 15 , further comprising:

etching the spacer after epitaxially growing the epitaxy layer; and

forming a semiconductor layer over the etched spacer.

17. The method of claim 16 , wherein forming the semiconductor layer is performed such that a portion of the semiconductor layer is formed over a top surface of the epitaxy layer.

18. The method of claim 16 , wherein forming the semiconductor layer is performed such that a portion of the semiconductor layer is formed over a top surface of the second portion of the first semiconductor substrate.

19. The method of claim 13 , wherein a top surface of the first semiconductor substrate and a top surface of the second semiconductor substrate have different crystal orientations.

20. The method of claim 13 , further comprising:

forming a conformal layer over the capping liner before forming the isolation filler.