Placement-based congestion-aware logic restructuring
Systems and techniques for optimizing an integrated circuit (IC) design are described. Some embodiments can transform a circuit design into a logically-equivalent circuit design by: (1) creating a Wire-Length-Area Model (WLAM) for a portion of a first circuit design, (2) creating a second circuit design by replacing the portion of the first circuit design by the WLAM, (3) placing and routing the second circuit design to obtain a placed-and-routed second circuit design, and (4) creating a third circuit design that is logically-equivalent to the first circuit design based on the placed-and-routed second circuit design.
1. A non-transitory computer-readable storage medium storing instructions for an integrated circuit (IC) design tool that, when executed by a computer, cause the computer to perform a method for transforming a circuit design into a logically-equivalent circuit design, the method comprising:
creating a second circuit design based on a first circuit design by:
identifying a set of Commutative-Associative Gate Trees (CAGTs) in the first circuit design; and
for each CAGT in the set of CAGTs, (1) identifying a set of Maximal Commutative-Associative Logic Functions (MCALFs) in the CAGT, (2) creating a Wire-Length-Area Model (WLAM) for the set of MCALFs, and (3) replacing the CAGT with the WLAM;
placing and routing the second circuit design to obtain a placed-and-routed second circuit design; and
creating a third circuit design that is logically-equivalent to the first circuit design by replacing each WLAM in the second circuit design by a logic network that is logically-equivalent to the CAGT that was replaced by the WLAM.
2. The non-transitory computer-readable storage medium of claim 1 , wherein placing and routing the second circuit design to obtain a placed-and-routed second circuit design comprises using a Steiner router.
3. The non-transitory computer-readable storage medium of claim 2 , wherein creating the third circuit design that is logically-equivalent to the first circuit design by replacing each WLAM in the second circuit design by a logic network that is logically-equivalent to the CAGT that was replaced by the WLAM comprises placing logic gates on Steiner points in the placed-and-routed second circuit design.
4. The non-transitory computer-readable storage medium of claim 1 , wherein performing placement and routing on the third circuit design results in substantially less routing congestion than performing placement and routing on the first circuit design.
5. The non-transitory computer-readable storage medium of claim 1 , wherein timing metrics, leakage power metrics, and area metrics of the third circuit design are optimized by (1) applying logically-equivalent transformations to portions of the third circuit design, (2) resizing one or more circuit elements in the third circuit design, and/or (3) performing rip-up and reroute operations on one or more nets in the third circuit design.
6. An apparatus, comprising:
a processor; and
a non-transitory computer-readable storage medium storing instructions for an integrated circuit (IC) design tool that, when executed by the processor, cause the apparatus to perform a method for transforming a circuit design into a logically-equivalent circuit design, the method comprising:
creating a second circuit design based on a first circuit design by:
identifying a set of Commutative-Associative Gate Trees (CAGTs) in the first circuit design; and
for each CAGT in the set of CAGTs, (1) identifying a set of Maximal Commutative-Associative Logic Functions (MCALFs) in the CAGT, (2) creating a Wire-Length-Area Model (WLAM) for the set of MCALFs, and (3) replacing the CAGT with the WLAM;
placing and routing the second circuit design to obtain a placed-and-routed second circuit design; and
creating a third circuit design that is logically-equivalent to the first circuit design by replacing each WLAM in the second circuit design by a logic network that is logically-equivalent to the CAGT that was replaced by the WLAM.
7. The apparatus of claim 6 , wherein placing and routing the second circuit design to obtain a placed-and-routed second circuit design comprises using a Steiner router.
8. The apparatus of claim 7 , wherein creating the third circuit design that is logically-equivalent to the first circuit design by replacing each WLAM in the second circuit design by a logic network that is logically-equivalent to the CAGT that was replaced by the WLAM comprises placing logic gates on Steiner points in the placed-and-routed second circuit design.
9. The apparatus of claim 6 , wherein performing placement and routing on the third circuit design results in substantially less routing congestion than performing placement and routing on the first circuit design.
10. The apparatus of claim 6 , wherein timing metrics, leakage power metrics, and area metrics of the third circuit design are optimized by (1) applying logically-equivalent transformations to portions of the third circuit design, (2) resizing one or more circuit elements in the third circuit design, and/or (3) performing rip-up and reroute operations on one or more nets in the third circuit design.
11. A method for transforming a circuit design into a logically-equivalent circuit design, comprising:
creating a second circuit design based on a first circuit design by:
identifying a set of Commutative-Associative Gate Trees (CAGTs) in the first circuit design; and
for each CAGT in the set of CAGTs, (1) identifying a set of Maximal Commutative-Associative Logic Functions (MCALFs) in the CAGT, (2) creatine a Wire-Length-Area Model (WLAM) for the set of MCALFs, and (3) replacing the CAGT with the WLAM;
placing and routing the second circuit design to obtain a placed-and-routed second circuit design; and
creating a third circuit design that is logically-equivalent to the first circuit design by replacing each WLAM in the second circuit design by a logic network that is logically-equivalent to the CAGT that was replaced by the WLAM.
12. The method of claim 11 , wherein placing and routing the second circuit design to obtain a placed-and-routed second circuit design comprises using a Steiner router.
13. The method of claim 12 , wherein creating the third circuit design that is logically-equivalent to the first circuit design by replacing each WLAM in the second circuit design by a logic network that is logically-equivalent to the CAGT that was replaced by the WLAM comprises placing logic gates on Steiner points in the placed-and-routed second circuit design.
14. The method of claim 11 , wherein performing placement and routing on the third circuit design results in substantially less routing congestion than performing placement and routing on the first circuit design.
15. The method of claim 11 , wherein timing metrics, leakage power metrics, and area metrics of the third circuit design are optimized by (1) applying logically-equivalent transformations to portions of the third circuit design, (2) resizing one or more circuit elements in the third circuit design, and/or (3) performing rip-up and reroute operations on one or more nets in the third circuit design.