Forming a contact for a tall fin transistor
View Patent ↗A method of making a semiconductor device includes forming a recessed fin in a substrate, the recessed fin being substantially flush with a surface of the substrate; performing an epitaxial growth process over the recessed fin to form a source/drain over the recessed fin; and disposing a conductive metal around the source/drain.
1. A semiconductor device, comprising:
a recessed fin patterned in a substrate between a first isolation region and a second isolation region, a first lateral sidewall of the recessed fin arranged in contact with the first isolation region and a second lateral sidewall of the recessed fin arranged in contact with the second isolation region;
a discrete epitaxial growth arranged over the recessed fin to form a discrete source/drain, the discrete source/drain arranged in contact with only a top surface of the recessed fin, with the first and second lateral sidewalls contacting the first and second isolation regions, and the discrete epitaxial growth having a width that is wider than a width of the recessed fin; and
a metal contact surrounding the discrete epitaxial growth, the metal directly contacting the isolation regions.
2. The semiconductor device of claim 1 , wherein a top surface of the recessed fin is flush with a top surface of the isolation regions.
3. The semiconductor device of claim 1 , wherein the recessed fin has a uniform height along a length of the recessed fin.
4. The semiconductor device of claim 1 , wherein the source/drain has a height in a range from about 20 to about 120 nanometers (nm).
5. The semiconductor device of claim 1 , further comprising a conductive metal surrounding the source/drain along three sidewalls.
6. The semiconductor device of claim 5 , further comprising a wrap-around silicide layer between the conductive metal and the discrete epitaxial growth.
7. The semiconductor device of claim 6 , wherein the wrap-around silicide layer is titanium silicide, tungsten silicide, cobalt silicide, nickel silicide, molybdenum silicide, platinum silicide, or any combination thereof.
8. The semiconductor device of claim 5 , wherein the conductive metal is aluminum, platinum, aluminum, platinum, gold, tungsten, titanium, or any combination thereof.
9. The semiconductor device of claim 1 , wherein a thickness of the discrete epitaxial growth is in a range from about 40 to about 70 nm.
10. The semiconductor device of claim 1 , further comprising another epitaxial growth over another adjacent recessed fin.
11. The semiconductor device of claim 10 , wherein the epitaxial growths are discrete and each surrounded by the conductive metal along three sidewalls.
12. The semiconductor device of claim 11 , further comprising a metal silicide layer between the conductive metal and the epitaxial growth.
13. The semiconductor device of claim 1 , wherein the recessed fin has a height in a range from about 20 to about 120 nm.
14. The semiconductor device of claim 13 , wherein the recessed fin has a height in a range from about 40 to about 70 nm.
15. The semiconductor device of claim 9 , wherein the epitaxial growth has a width in a range from about 10 to about 50 nm.
16. The semiconductor device of claim 1 , wherein the discrete epitaxial growth comprise silicon.
17. The semiconductor device of claim 16 , wherein the silicon is doped.
18. The semiconductor device of claim 17 , wherein the dopant is an n-type dopant.
19. The semiconductor device of claim 17 , wherein the dopant is a p-type dopant.
20. The semiconductor device of claim 1 , wherein the isolation regions comprise silicon dioxide.