Fabrication method of high aspect ratio solder bumping with stud bump and injection molded solder, and flip chip joining with the solder bump
A technique for fabricating bumps on a substrate is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared. A bump base is formed on each pad of the substrate. Each bump base has a tip extending outwardly from the corresponding pad. A resist layer is patterned on the substrate to have a set of holes through the resist layer. Each hole is aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad. The set of the holes in the resist layer is filled with conductive material to form a set of bumps on the substrate. The resist layer is stripped from the substrate with leaving the set of the bumps.
1. A method for fabricating bumps on a substrate, the method comprising:
preparing a substrate including a set of pads formed on a surface thereof;
forming a bump base on each pad of the substrate, each bump base having a body and a tip extending outwardly from the corresponding pad;
patterning a resist layer on the substrate to have a set of holes through the resist layer, each hole being aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad;
filling the set of the holes with conductive material to form a set of bumps on the substrate; and
stripping the resist layer from the substrate leaving the set of the bumps.
2. The method of claim 1 , wherein the conductive material is solder material and injected into each hole in a molten state and the set of the bumps is a set of solder capped bumps each being made of material of the bump base formed on the substrate and the solder material filled into the hole.
3. The method of claim 1 , wherein each bump base extends the tip in a direction approximately normal to the surface of the substrate, and the resist layer has a thickness aligned to the levels of the tips of the bump bases.
4. The method of claim 1 , wherein each bump base is a stud bump formed by wire bonding.
5. The method of claim 4 , wherein each stud bump is selected from the group consisting of an Au stud bump, a bare Cu stud bump, a Pd-coated Cu stud bump and an Ag stud bump.
6. The method of claim 4 , wherein each stud bump is a Cu stud bump having a protection layer formed on a surface thereof.
7. The method of claim 4 , wherein the method further comprises:
flattening the tips of the stud bumps by coining.
8. The method of claim 1 , wherein patterning the resist layer on the substrate comprises:
applying a photoresist material on the substrate; and
exposing and developing the photoresist material so as to open holes through the photoresist material with aligning with the pads, the photoresist material having the holes corresponding to the resist layer having the set of the holes.
9. A method for interconnecting a semiconductor device with external circuitry by bumps, the method comprising:
performing the method of claim 1 to prepare a semiconductor device including at least a part of the bumps formed on the surface of the substrate; and
preparing external circuitry having a set of electrodes formed on a surface thereof;
mounting the semiconductor device to the external circuitry such that the bumps of the semiconductor device are in contact with the electrodes of the external circuitry, respectively.
10. The method of claim 9 , wherein the bumps of the semiconductor device includes a set of solder capped bumps each being made of material of the bump base and solder material.
11. The method of claim 9 , wherein the external circuitry has a layer having a set of via holes aligned with the electrodes, the bumps of the semiconductor device are inserted into the via holes of the external circuitry, respectively, when mounting the semiconductor device to the external circuitry.
12. The method of claim 11 , wherein the external circuitry is provided as a form of an organic substrate having an optical waveguide integrated thereon as the layer having the set of via holes.
13. The method of claim 9 , wherein the semiconductor device is mounted to the external circuitry without forming a pre-solder on each electrode of the external circuitry.
14. A structure comprising:
a substrate including a set of pads formed on a surface thereof; and
a set of bumps formed on the pads, each bump being fabricated by:
forming a bump base on each pad, each bump base having a body and a tip extending outwardly from the corresponding pad; and
filling conductive material into a set of holes of a resist layer patterned on the substrate, each hole being aligned with the corresponding pads and having space surrounding the tip of the bump base formed on the corresponding pad.
15. The structure of claim 14 , wherein the conductive material is solder material and solidified in each hole and the set of the bumps is a set of solder capped bumps each being made of the material of the bump base formed on the substrate and the solder material filled into the hole.