CMOS FinFET structures including work-function materials having different proportions of crystalline orientations and methods of forming the same
A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.
1. A method comprising:
forming an n-type transistor comprising:
forming a first semiconductor fin protruding from a substrate;
forming a first dummy gate over the first semiconductor fin;
forming first gate spacers on sidewalls of the first dummy gate;
removing the first dummy gate and forming a first gate stack over the first semiconductor fin to replace the first dummy gate, wherein forming the first gate stack comprises:
depositing a first gate dielectric layer over the first semiconductor fin;
forming a capping layer material over the first gate dielectric layer; and
after forming the capping layer material, depositing a work-function material over the capping layer material using a first set of process parameters, wherein the first set of process parameters is associated with forming the work-function material having a first work-function, wherein the first work-function is associated with a first proportion of a first crystalline orientation and a second crystalline orientation of the work-function material; and
forming a p-type transistor comprising:
forming a second semiconductor fin protruding from the substrate;
forming a second dummy gate over the second semiconductor fin;
forming second gate spacers on sidewalls of the second dummy gate;
removing the first second dummy gate and forming a second gate stack over the second semiconductor fin to replace the second dummy gate, wherein forming the second gate stack comprises:
depositing a second gate dielectric layer over the second semiconductor fin;
forming the capping layer material over the second gate dielectric layer; and
after forming the capping layer material, depositing the work-function material over the capping layer material using a second set of process parameters, wherein the second set of process parameters is associated with forming the work-function material having a second work-function, wherein the second work-function is associated with a second proportion of the first crystalline orientation and the second crystalline orientation of the work-function material.
2. The method of claim 1 , further comprising diffusing a dopant into the work-function material.
3. The method of claim 2 , wherein the dopant is fluorine.
4. The method of claim 2 , wherein the first crystalline orientation has a first diffusibility of the dopant and the second crystalline orientation has a second diffusibility of the dopant that is different from the first diffusibility.
5. The method of claim 1 , wherein the work-function material is TiN.
6. The method of claim 1 , wherein the work-function material is deposited to a thickness less than about 20 Å.
7. The method of claim 1 , wherein the first crystalline orientation is (111) and the second crystalline orientation is (200).
8. The method of claim 1 , wherein the first proportion is a ratio between the amount of the first crystalline orientation present in the work-function material of the n-type transistor and the amount of the second crystalline orientation present in the work-function material of the n-type transistor.
9. A method comprising:
forming a first transistor, comprising:
forming a first fin in a substrate comprising a first channel region;
forming a first gate dielectric layer over the first channel region;
forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer comprises conformally depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations; and
depositing a bulk metal over the first work-function layer; and
forming a second transistor, comprising:
forming a second fin in the substrate comprising a second channel region;
forming a second gate dielectric layer over the second channel region;
forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer comprises conformally depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations; and
depositing the bulk metal over the second work-function layer.
10. The method of claim 9 , further comprising diffusing a dopant into the work-function material, wherein the dopant diffuses into regions of the work-function material having a first crystalline orientation more than the dopant diffuses into regions of the work-function material having a second crystalline orientation.
11. The method of claim 10 , wherein the dopant is fluorine.
12. The method of claim 9 , wherein the first process conditions comprise a first temperature, wherein the first temperature is between about 320° C. and about 380° C.
13. The method of claim 9 , further comprising annealing the work-function material.
14. The method of claim 9 , wherein the first transistor is n-type and the second transistor is p-type.
15. A method comprising:
forming an n-type transistor, comprising:
forming a first fin extending from a semiconductor substrate;
forming a first gate dielectric layer on the first fin;
forming a first capping layer on the first gate dielectric layer;
forming a first work-function layer on the first capping layer, wherein the first work-function layer extends conformally over the first capping layer; and
forming a bulk metal on the first work-function layer, and
forming a p-type transistor, comprising:
forming a second fin extending from the semiconductor substrate;
forming a second gate dielectric layer on the second fin;
forming a second capping layer on the first gate dielectric layer;
forming a second work-function layer on the second capping layer, wherein the second work-function layer extends conformally over the second capping layer, wherein the first work-function layer and the second work-function layer comprise the same work-function material, and wherein the first work-function layer has a first proportion of crystalline orientations and the second work-function layer has a second proportion of crystalline orientations; and
forming the bulk metal on the second work-function layer.
16. The method of claim 15 , wherein the work-function material comprises TiN.
17. The method of claim 15 , wherein the work-function material comprises a dopant, wherein the dopant has a greater concentration in first regions of the work-function material having a first crystalline orientation than in second regions of the work-function material having a second crystalline orientation.
18. The method of claim 17 , wherein the dopant is fluorine.
19. The method of claim 17 , wherein the first crystalline orientation is (111) and the second crystalline orientation is (200).
20. The method of claim 15 , wherein the first work-function layer has a thickness of less than about 20 Å.