Method and device for forming metal gate electrodes for transistors
A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.
1. A semiconductor device, comprising:
a first source/drain and a second source/drain;
a semiconductor structure disposed between the first source/drain and the second source/drain;
a gate dielectric disposed over the semiconductor structure;
a metal-containing gate electrode disposed over the gate dielectric, wherein at least a portion of an upper surface of the metal-containing gate electrode is curved;
a first dielectric structure, wherein a bottom surface of the first dielectric structure is disposed over the upper surface of the metal-containing gate electrode; and
a second dielectric structure disposed over the metal-containing gate electrode, wherein the second dielectric structure extends through the first dielectric structure vertically.
2. The semiconductor device of claim 1 , wherein the first dielectric structure and the second dielectric structure have different material compositions.
3. The semiconductor device of claim 2 , wherein:
the first dielectric structure contains zirconium oxide, yttrium silicon oxide, or silicon oxy-carbide;
the second dielectric structure contains silicon nitride or silicon oxide.
4. The semiconductor device of claim 1 , wherein the first dielectric structure has a cross-sectional profile that resembles a vertically-flipped letter “L”.
5. The semiconductor device of claim 1 , wherein a bottommost surface of the first dielectric structure is more elevated vertically than a bottommost surface of the second dielectric structure.
6. The semiconductor device of claim 1 , further comprising gate spacers disposed around the metal-containing gate electrode laterally, wherein a portion of the gate spacers is in direct physical contact with the first dielectric structure.
7. The semiconductor device of claim 6 , wherein the gate spacers have a lower dielectric constant than the first dielectric structure.
8. The semiconductor device of claim 6 , wherein:
the first dielectric structure includes an upper portion and a lower portion;
a bottom surface of the upper portion of the first dielectric structure is disposed over an upper surface of the portion of the gate spacers; and
a first side surface of the lower portion of the first dielectric structure is disposed on a sidewall of the portion of the gate spacers.
9. The semiconductor device of claim 8 , further comprising an interlayer dielectric (ILD) disposed over the first source/drain, wherein:
a first side surface of the upper portion of the first dielectric structure is in direct physical contact with the ILD;
a second side surface of the upper portion of the first dielectric structure is in direct physical contact with the second dielectric structure; and
a second side surface of the lower portion of the first dielectric structure is in direct physical contact with the second dielectric structure.
10. The semiconductor device of claim 1 , wherein the first dielectric structure and the second dielectric structure have substantially co-planar upper surfaces.
11. The semiconductor device of claim 1 , wherein the first dielectric structure has more rounded bottom surfaces than the second dielectric structure.
12. The semiconductor device of claim 1 , wherein:
the metal-containing gate electrode includes a work function metal layer and a first metal layer disposed over the work function metal layer;
the first dielectric structure is in direct contact with the work function metal layer and the first metal layer; and
the second dielectric structure is in direct contact with the first metal layer but not with the work function metal layer.
13. A semiconductor device, comprising:
a first source/drain region and a second source/drain region;
an interlayer dielectric (ILD) disposed over the first source/drain region or over the second source/drain region;
a semiconductor-containing structure disposed between the first source/drain region and the second source/drain region;
a gate dielectric layer disposed over the semiconductor-containing structure;
a metal-containing gate electrode disposed over the gate dielectric layer;
a gate spacer disposed around the metal-containing gate electrode laterally; and
a high-k dielectric component disposed over the metal-containing gate electrode;
wherein:
the high-k dielectric component has: a first side surface, a second side surface opposite the first side surface, a first bottom surface, and a second bottom surface less elevated vertically than the first bottom surface;
the first side surface is in direct contact with the ILD;
the second side surface is longer than the first side surface;
the first bottom surface is in direct contact with the gate spacer; and
the second bottom surface is in direct contact with the metal-containing gate electrode.
14. The semiconductor device of claim 13 , further comprising:
an interlayer dielectric (ILD) disposed over the first source/drain region or over the second source/drain region; and
a dielectric layer disposed over the metal-containing gate electrode;
wherein
the high-k dielectric component is disposed between the ILD and the dielectric layer;
the ILD is in direct contact with the first side surface of the high-k dielectric component; and
the dielectric layer is in direct contact with the second side surface of the high-k dielectric component.
15. The semiconductor device of claim 14 , wherein the high-k dielectric component has a greater dielectric constant than the dielectric layer.
16. The semiconductor device of claim 13 , wherein an upper surface of the gate spacer is more elevated vertically than the second bottom surface of the high-k dielectric component.
17. The semiconductor device of claim 13 , wherein the second bottom surface of the high-k dielectric component is more curved than the first bottom surface of the high-k dielectric component.
18. A semiconductor device, comprising:
a first source/drain region and a second source/drain region;
a fin structure located between the first source/drain region and the second source/drain region in a cross-sectional side view;
a gate dielectric located over the fin structure in the cross-sectional side view;
a metal-containing gate electrode located over the gate dielectric in the cross-sectional side view;
an interlayer dielectric (ILD) located over the first source/drain region and over the second source/drain region in the cross-sectional side view;
a dielectric component located over the metal-containing gate electrode in the cross-sectional side view; and
a gate helmet located over and protrudes downwardly into the metal-containing gate electrode and between the ILD and the dielectric component in the cross-sectional side view, wherein the gate helmet has a greater dielectric constant than the dielectric component and the ILD, and wherein a shape of the gate helmet in the cross-sectional side view resembles a vertically flipped letter “L”.
19. The semiconductor device of claim 18 , further comprising gate spacers located between the ILD and the metal-containing gate electrode in the cross-sectional side view, wherein the gate spacers are in direct contact with a portion of a bottom surface of the gate helmet and with a portion of a side surface of the gate helmet.
20. The semiconductor device of claim 18 , wherein:
a bottommost surface of the gate helmet is more curved than a bottommost surface of the dielectric component; and
the bottommost surface of the gate helmet is more elevated vertically than a bottom surface of the ILD.