Methods, apparatus and system for self-aligned metal hard masks
At least one method, apparatus and system disclosed herein involves forming semiconductor devices comprising vertically aligned gates, metal hard masks, and nitride regions. The semiconductor device may contain a semiconductor substrate; a gate disposed on the semiconductor substrate; a metal hard mask vertically aligned with the gate; a nitride region vertically aligned with the gate and the metal hard mask; and source/drain (S/D) regions disposed in proximity to the gate.
1. A method, comprising:
forming a gate disposed on a semiconductor substrate and having a first side and a second side;
forming a metal hard mask disposed on the gate and having a first side and second side, wherein the first side of the metal hard mask is vertically aligned with the first side of the gate and the second side of the metal hard mask is vertically aligned with the second side of the gate;
forming a nitride region disposed on the metal hard mask and having a first side and second side, wherein at least a portion of the first side of the nitride region is vertically aligned with the first sides of the gate and the metal hard mask, at least a portion of the second side of the nitride region is vertically aligned with the second sides of the gate and the metal hard mask; and the nitride region is T-shaped;
forming a spacer disposed on the first sides of the gate and the metal hard mask and on the second sides of the gate and the metal hard mask, wherein a top of the spacer is above a top of the metal hard mask;
forming a first source/drain (S/D) region disposed in proximity to the first side of the gate; and
forming a second S/D region disposed in proximity to the second side of the gate.
2. The method of claim 1 , wherein the metal is tungsten.
3. The method of claim 1 , wherein the gate is a high-k metal gate.
4. The method of claim 1 , wherein the nitride is silicon nitride.
5. The method of claim 1 , wherein either:
the entire first side of the nitride region is vertically aligned with the first side of the gate and the first side of the metal hard mask; or
the entire second side of the nitride region is vertically aligned with the second side of the gate and the second side of the metal hard mask.
6. The method of claim 1 , wherein either:
the first side of the nitride region has a lower portion vertically aligned with the first side of the gate and the first side of the metal hard mask and an upper portion lacking vertical alignment with the first side of the gate and the first side of the metal hard mask;
the second side of the nitride region has a lower portion vertically aligned with the second side of the gate and the second side of the metal hard mask and an upper portion lacking vertical alignment with the second side of the gate and the second side of the metal hard mask; or
both.
7. A system, comprising:
a semiconductor device processing system to manufacture a semiconductor device; and
a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of the semiconductor device processing system;
wherein the semiconductor device processing system is adapted to:
form a gate disposed on a semiconductor substrate and having a first side and a second side;
form a metal hard mask disposed on the gate and having a first side and second side, wherein the first side of the metal hard mask is vertically aligned with the first side of the gate and the second side of the metal hard mask is vertically aligned with the second side of the gate;
form a nitride region disposed on the metal hard mask and having a first side and second side, wherein a lower portion of the first side of the nitride region is vertically aligned with the first sides of the gate and the metal hard mask, a lower portion of the second side of the nitride region is vertically aligned with the second sides of the gate and the metal hard mask, and the nitride region is T-shaped;
form a spacer disposed on the first sides of the gate and the metal hard mask and on the second sides of the gate and the metal hard mask, wherein a top of the spacer is above a top of the metal hard mask;
form a first source/drain (S/D) region disposed in proximity to the first side of the gate; and
form a second S/D region disposed in proximity to the second side of the gate.
8. The system of claim 7 , wherein the semiconductor device processing system is adapted to provide the metal hard mask as tungsten.
9. The system of claim 7 , wherein the semiconductor device processing system is adapted to provide the gate as a high-k metal gate.
10. The system of claim 7 , wherein the semiconductor device processing system is adapted to deposit the nitride as silicon nitride.
11. The system of claim 7 , wherein either:
the entire first side of the nitride region is vertically aligned with the first side of the gate and the first side of the metal hard mask; or
the entire second side of the nitride region is vertically aligned with the second side of the gate and the second side of the metal hard mask.
12. The system of claim 7 , wherein either:
the first side of the nitride region has a lower portion vertically aligned with the first side of the gate and the first side of the metal hard mask and an upper portion lacking vertical alignment with the first side of the gate and the first side of the metal hard mask;
the second side of the nitride region has a lower portion vertically aligned with the second side of the gate and the second side of the metal hard mask and an upper portion lacking vertical alignment with the second side of the gate and the second side of the metal hard mask; or
both.
13. A method, comprising:
providing a semiconductor structure comprising:
a semiconductor substrate;
a gate disposed on the semiconductor substrate and having a first side and a second side;
a metal hard mask disposed on the gate and having a first side and second side, wherein the first side of the metal hard mask is vertically aligned with the first side of the gate and the second side of the metal hard mask is vertically aligned with the second side of the gate;
a spacer disposed on the first sides of the gate and the metal hard mask and on the second sides of the gate and the metal hard mask;
a first source/drain (S/D) region disposed in proximity to the first side of the gate;
a second S/D region disposed in proximity to the second side of the gate;
a contact etch stop layer (CESL) disposed on the first S/D region, the second S/D region, and on the spacer; and
an interlayer dielectric (ILD) disposed on the CESL above the first S/D region and above the second S/D region;
removing the ILD above the first S/D region and above the second S/D region, to yield a first trench above the first S/D region and a second trench above the second S/D region;
filling the first trench and the second trench with amorphous silicon;
recessing the metal hard mask below a top of the spacer, to yield a recess; and
filling the recess with a nitride.
14. The method of claim 13 , further comprising:
removing the amorphous silicon from the first trench and the second trench; and
removing the CESL from the first S/D region, the second S/D region, and the spacer.
15. The method of claim 13 , wherein the metal is tungsten.
16. The method of claim 13 , wherein the gate is a high-k metal gate.
17. The method of claim 13 , wherein the nitride is silicon nitride.