Method and structure of forming FinFET contact

1. A method for fabricating an FET semiconductor structure, the method comprising:

forming, on a substrate, at least one source/drain region of at least one FET, the at least one source/drain region being formed adjacent to a gate stack region of the at least one FET;

depositing conductive contact material directly on and fully covering the at least one source/drain region to form a source/drain contact for the at least one source/drain region, the source/drain contact being disposed adjacent to, and contacting, a vertical sidewall of a gate spacer of a gate stack in the gate stack region;

forming a reverse contact mask directly on and covering the source/drain contact, the reverse contact mask covering a limited horizontal area over the source/drain contact that is disposed directly over the at least one source/drain region, the limited horizontal area contacting, and horizontally extending along, less than a full horizontal length of the vertical sidewall of the gate spacer of the gate stack, the limited horizontal area less than fully covering the source/drain contact disposed directly over the at least one source/drain region;

etching the source/drain contact to create recesses in the source/drain contact where there is no reverse contact mask covering the source/drain contact; and

depositing dielectric material directly on, and filling therewith, the recesses.

2. The method of claim 1 , wherein the depositing dielectric material comprises depositing dielectric material directly on, and filling therewith, the recesses up to a top surface of the reverse contact mask, and further comprising:

performing, following the depositing dielectric material, a planarization process on the reverse contact mask and the dielectric material;

stripping the reverse contact mask from above the source/drain contact thereby leaving trenches over the source/drain contact; and

depositing conductive material directly on and filling the trenches to form trench contacts to complete local metallization of interconnects on the source/drain contact.

3. The method of claim 1 , wherein the at least one source/drain region includes a plurality of merged source/drain regions of a plurality of FETs.

4. The method of claim 1 , wherein the at least one FET is a plurality of FETs, and wherein the at least one source/drain region being formed adjacent to first gate stack region and second gate stack region of two of the plurality of FETs, each of the first gate stack region and second gate stack region including a respective first gate stack with gate conductor and first gate spacer and second gate stack with gate conductor and second gate spacer, the first gate spacer and second gate spacer respectively separate and electrically insulate the first gate stack and second gate stack from an adjacent source/drain contact of the at least one source/drain region, and wherein the method comprising:

forming the reverse contact mask directly on and covering the source/drain contact from the first gate stack with gate conductor and first gate spacer to the second gate stack with gate conductor and second gate spacer, the reverse contact mask covering a limited horizontal area over the source/drain contact that is disposed directly over the at least one source/drain region, the limited horizontal area contacting, and horizontally extending along, less than a full horizontal length of the vertical sidewall of each of the first gate spacer and the second gate spacer, the limited horizontal area less than fully covering the source/drain contact disposed directly over the at least one source/drain region.

5. The method of claim 1 , wherein the forming of the at least one source/drain region comprises forming at least one FinFET semiconductor device.

6. The method of claim 5 , wherein the forming of the FinFET semiconductor device comprises forming a plurality of fins in the at least one source/drain region for the at least one FinFET semiconductor device.

7. The method of claim 1 , wherein the reverse contact mask comprising Nitride or Silicon Nitride.

8. A method for fabricating a source/drain contact in an FET semiconductor structure having the source/drain contact disposed directly on a source/drain region layer of a plurality of FETs, the source/drain region layer being adjacent to first and second gate stack region of two respective FETs in the plurality of FETs, each of the first gate stack region and second gate stack region including respective first gate stack with a first gate spacer and a second gate stack with a second gate spacer, the first and second gate spacers separating and insulating the respective first gate stack and second gate stack from an adjacent respective first and second opposing sides of the source/drain contact, the method comprising:

forming a reverse contact mask directly on and covering the source/drain contact from the first gate stack with the first gate spacer to the second gate stack with the second gate spacer, the reverse contact mask covering a limited horizontal area over the source/drain contact that is disposed directly over the source/drain region, the limited horizontal area contacting, and horizontally extending along, less than a full horizontal length of a vertical sidewall of each of the first gate spacer and the second gate spacer, the limited horizontal area less than fully covering the source/drain contact disposed directly over the source/drain region layer;

etching the source/drain contact to create recesses in the source/drain contact where there is no reverse contact mask directly on and covering the source/drain contact; and

depositing dielectric material directly on, and filling, the recesses.

9. The method of claim 8 , wherein the etching to create recesses in the source/drain contact forming a shape of the source/drain contact into an inverted “T” shape.

10. The method of claim 8 , wherein the dielectric material is oxide.

11. The method of claim 8 , wherein the source/drain contact comprises tungsten or cobalt.

12. The method of claim 8 , wherein the etching creates shallow recesses in the source/drain contact, where bottoms of the recesses stop in the source/drain contact vertically above the source/drain region layer.

13. The method of claim 8 , further comprising:

forming, on a substrate, the source/drain region layer including disposed directly thereon a plurality of fins of a plurality of FinFETs.