Memory device and method for fabricating the same
A memory device includes a semiconductor substrate, a bottom insulating layer disposed on the semiconductor substrate, a first conductive layer which is a selective epitaxial growth layer disposed on the bottom insulating layer; a plurality insulating layers disposed over the bottom insulating layer; a plurality of second conductive layers alternatively stacked the insulating layers and insulated from the first conductive layer; a contact plug passing through the bottom insulating layer and electrically contacting the semiconductor substrate with the first conductive layer; a channel layer disposed on at least one sidewall of at least one first through opening and electrically contact the contact plug, wherein the first through opening passes through the insulating layers, the second conductive layers, so as to expose the contact plug; and a memory layer disposed between the channel layer and the second conductive layers.
1. A memory device, comprising:
a semiconductor substrate;
a bottom insulating layer, disposed on the semiconductor substrate;
a first conductive layer, disposed on the bottom insulating layer, wherein the first conductive layer is a selective epitaxial growth layer;
a plurality of insulating layers, disposed over the first conductive layer;
a plurality of second conductive layers, insulated from the first conductive layer, wherein the second conductive layers and the insulating layers are alternatively stacked;
a contact plug, passing through the bottom insulating layer and electrically contacting the semiconductor substrate with the first conductive layer;
a channel layer, disposed on at least one sidewall of at least one first through opening and electrically contact the contact plug, wherein the first through opening passes through the insulating layers, the second conductive layers, so as to expose the contact plug; and
a memory layer, disposed between the channel layer and the second conductive layers.
2. The memory device according to claim 1 , wherein the first conductive layer has a top surface having a curved shape which is exposed from a second through opening, wherein the second through opening passes through the insulating layers and the second conductive layers.
3. The memory device according to claim 1 , further comprising a protection layer disposed on an exposed surface of the semiconductor substrate which is exposed from an second through opening, wherein the second through opening passes through the insulating layers and the second conductive layers, and the protection layer is disposed between the semiconductor substrate and the first conductive layer.
4. The memory device according to claim 3 , wherein the protection layer has an upper surface contacting the first conductive layer, and has a lower surface contacting the semiconductor substrate.
5. The memory device according to claim 1 , wherein the memory layer comprises an oxide-nitride-oxide (ONO) structure disposed on the sidewall of the first through opening and between the second conductive layers and the channel layer.
6. The memory device according to claim 1 , further comprising:
a dielectric spacer disposed on a sidewall of a second through opening, wherein the second through opening passes through the insulating layers and the second conductive layers, so as to expose the first conductive layer; and
a metal plug, disposed in the second through opening, electrically in contact with the first conductive layer and electrically insulated from the second conductive layers by the dielectric spacer.
7. The memory device according to claim 1 , wherein the contact plug has a top surface higher than a top surface of the first conductive layer.
8. The memory device according to claim 1 , further comprising:
a dielectric material filled into the first through opening in which at least one air gap is formed;
a bond pad disposed on the dielectric material; and
a capping layer covering the bond pad.