IP Library Granted Patent US 10,522,477
Granted Patent B2
US 10,522,477 · App. 15/810,602 · Granted Dec 31, 2019

Method of making package assembly including stress relief structures

Inventor: Hsien-Wei Chen (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L23/562H01L23/16H01L25/0655H01L23/5384H01L2224/16225H01L2224/32225H01L2224/73204H01L2924/3511
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,522,477
App. No.
15/810,602
Granted
Dec 31, 2019
Kind
B2
Abstract

A method of making a semiconductor package structure includes bonding a plurality of dies to a substrate, wherein a first die of the plurality of dies is larger than a second die of the plurality of dies. The method further includes adhering a first stress relief structure to the substrate at a corner of the substrate, wherein a distance between the first stress relief structure to a closest die of the plurality of dies to the first stress relief structure is a first distance. The method further includes adhering a second stress relief structure to the substrate along a single edge of the substrate, wherein a distance between the second stress relief structure to a closest die of the plurality of dies to the second stress relief structure is the first distance.

Claims (32)

1. A method of making a semiconductor package structure comprising:

bonding a plurality of dies to a substrate, wherein a first die of the plurality of dies is larger than a second die of the plurality of dies;

adhering a first stress relief structure to the substrate at a corner of the substrate, wherein a distance between the first stress relief structure to a closest die of the plurality of dies to the first stress relief structure is a first distance; and

adhering a second stress relief structure to the substrate along a single edge of the substrate, wherein a distance between the second stress relief structure to a closest die of the plurality of dies to the second stress relief structure is the first distance.

2. The method of claim 1 , wherein the adhering of the first stress relief structure comprises adhering the first stress relief structure to the substrate using an epoxy, urethane, polyurethane, or silicone elastomers.

3. The method of claim 1 , wherein the adhering of the first stress relief structure comprises curing an adhesive used to adhere the first stress relief structure to the substrate.

4. The method of claim 1 , wherein the adhering of the first stress relief structure comprises adhering the first stress relief structure to the substrate using an adhesive having a thermal conductivity greater than about 10 W/m° C.

5. The method of claim 1 , wherein the adhering of the first stress relief structure to the substrate comprises adhering the first stress relief structure at a location to establish the first distance greater than about 2 microns (μm).

6. The method of claim 1 , wherein the adhering of the second stress relief structure to the substrate comprises adhering the second stress relief structure comprising a same material as the first stress relief structure.

7. The method of claim 1 , wherein the adhering of the second stress relief structure to the substrate comprises adhering the second stress relief structure comprising a plurality of discontinuous segments.

8. The method of claim 1 , wherein the adhering of the first stress relief structure comprises adhering the first stress relief structure having an L-shape.

9. The method of claim 1 , wherein the adhering of the first stress relief structure to the substrate comprises coating an adhesive material on the substrate.

10. A method of making a semiconductor package structure comprising:

bonding a plurality of dies to a substrate, wherein a first die of the plurality of dies is larger than a second die of the plurality of dies;

depositing a stress relief material on the substrate;

patterning the stress relief material to define a first stress relief structure to the substrate at a corner of the substrate and a second stress relief structure along a single edge of the substrate, wherein a distance between the first stress relief structure to a closest die of the plurality of dies to the first stress relief structure is a first distance, and a distance between the second stress relief structure to a closest die of the plurality of dies to the second stress relief structure is the first distance.

11. The method of claim 10 , wherein the patterning of the stress relief material comprises a photolithography process.

12. The method of claim 10 , wherein the patterning of the stress relief material comprises an etching process.

13. The method of claim 10 , wherein the depositing of the stress relief material comprises depositing the stress relief material having a thermal conductivity greater than about 20 W/m° C.

14. The method of claim 10 , wherein the patterning of the stress relief material comprises defining the second stress relief structure comprising a plurality of discontinuous segments.

15. The method of claim 10 , wherein the patterning of the stress relief material comprises defining the first stress relief structure comprising an L-shape.

16. A method of making a semiconductor package structure comprising:

bonding a plurality of dies to a substrate, wherein a first die of the plurality of dies is larger than a second die of the plurality of dies;

defining a first stress relief structure on the substrate, wherein a distance between the first stress relief structure to a closest die of the plurality of dies to the first stress relief structure is a first distance; and

defining a second stress relief structure on the substrate, wherein a distance between the second stress relief structure to a closest die of the plurality of dies to the second stress relief structure is the first distance, and the second stress relief structure is discontinuous with respect to the first stress relief structure.

17. The method of claim 16 , wherein the defining of the first stress relief structure comprises:

depositing a stress relief material on the substrate; and

patterning the stress relief material.

18. The method of claim 16 , wherein the defining of the first stress relief structure comprises adhering the first stress relief structure to the substrate.

19. The method of claim 16 , wherein the defining of the first stress relief structure comprises:

defining the first stress relief structure adjacent to a corner of at least one die of the plurality of dies, wherein the first stress relief structure comprises a first portion extending along a first side of the at least one die and a second portion extending along a second side of the at least one die, and the first portion is continuous with the second portion.

20. The method of claim 16 , wherein the defining of the second stress relief structure comprises defining the second stress relief structure along a single edge of the substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 13, 2017
From: CHEN, HSIEN-WEI
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 044105/0442 →
Continuity (3)
Continuation 15062570 · Mar 7, 2016
Division 13673703 · Nov 9, 2012
Related Publication 20180068960A1 · Mar 8, 2018
Cited By (2)
US 12,394,738 US 12,543,571