IP Library Granted Patent US 10,901,885
Granted Patent B2
US 10,901,885 · App. 15/813,967 · Granted Jan 26, 2021

Memory device and non-transitory computer readable recording medium

Inventor: Shinichi Kanno (Tokyo, JP)
Assignee: Toshiba Memory Corporation
G06F12/0246G06F12/02G06F2212/1036G06F2212/222G06F2212/7201G06F2212/7209
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Quick Facts
Patent No.
US 10,901,885
App. No.
15/813,967
Granted
Jan 26, 2021
Kind
B2
Abstract

According to one embodiment, a memory device includes a nonvolatile memory, address translation unit, generation unit, and reception unit. The nonvolatile memory includes erase unit areas. Each of the erase unit areas includes write unit areas. The address translation unit generates address translation information relating a logical address of write data written to the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory. The generation unit generates valid/invalid information indicating whether data written to the erase unit areas is valid data or invalid data. The reception unit receives deletion information including a logical address indicative of data to be deleted in the erase unit area.

Claims (55)

1. A memory device, comprising:

a nonvolatile memory; and

a controller electrically connected to the nonvolatile memory and configured to:

generate first information including a logical address associated with valid data written in a first area of the nonvolatile memory, the first area being a candidate for garbage collection,

transmit the first information to a host device, and

in response to receiving, from the host device, second information that is received after the first information is transmitted to the host device, the second information specifying a logical address associated with data to be deleted amongst the valid data in the first area,

select first data that is the valid data written in the first area and not specified in the second information as the data to be deleted,

select second data that is the valid data written in the first area and specified in the second information as the data to be deleted, and

perform the garbage collection on the first area such that the first data is copied to a second area of the nonvolatile memory but the second data is not copied to the second area of the nonvolatile memory, the second area being different from the first area.

2. The memory device of claim 1 , wherein

the controller is further configured to generate third information indicating whether data written in the nonvolatile memory is valid or invalid, and generate the first information based on the third information.

3. The memory device of claim 2 , wherein

the controller is further configured to generate fourth information relating a logical address of write data written in the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory, and generate the third information based on the fourth information.

4. The memory device of claim 2 , wherein

the controller is configured to perform, based on the second information and the third information, the garbage collection on the first area.

5. The memory device of claim 2 , wherein

the controller is configured to select the first area, and perform the garbage collection on the selected first area.

6. The memory device of claim 5 , wherein

the controller is configured to select the first area based on the third information.

7. The memory device of claim 5 , wherein

the controller is configured to select the first area based on the second information and the third information.

8. The memory device of claim 1 , wherein

the valid data is updated data in a case where update of the data written in the nonvolatile memory is performed, and

the data to be deleted is data for which a delete command has been issued.

9. A system comprising the memory device of claim 1 and the host device of claim 1 , wherein

the host device is configured to:

receive the first information,

after receiving the first information, generate the second information based on the first information, and

transmit the generated second information to the memory device.

10. A control method of a memory device, the control method comprising:

generating first information including a logical address associated with valid data written in a first area of a nonvolatile memory included in the memory device, the first area being a candidate for garbage collection;

transmitting the first information to a host device communicating with the memory device; and

in response to receiving, from the host device, second information that is received after the first information is transmitted to the host device, the second information specifying a logical address associated with data to be deleted amongst the valid data in the first area,

selecting first data that is the valid data written in the first area and not specified in the second information as the data to be deleted,

selecting second data that is the valid data written in the first area and specified in the second information as the data to be deleted, and

performing the garbage collection on the first area such that the first data is copied to a second area of the nonvolatile memory but the second data is not copied to the second area of the nonvolatile memory, the second area being different from the first area.

11. The control method of claim 10 , further comprising:

generating third information indicating whether data written in the nonvolatile memory is valid or invalid, wherein

the first information is generated based on the third information.

12. The control method of claim 11 , further comprising:

generating fourth information relating a logical address of write data written in the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory, wherein

the third information is generated based on the fourth information.

13. The control method of claim 12 , wherein, the garbage collection on the first area is performed based on the second information and the third information.

14. The control method of claim 11 , further comprising:

selecting the first area, wherein

the garbage collection is performed on the selected first area.

15. The control method of claim 14 , wherein the first area is selected based on the third information.

16. The control method of claim 14 , wherein the first area is selected based on the second information and the third information.

17. The control method of claim 10 , wherein

the valid data is updated data in a case where update of the data written in the nonvolatile memory is performed, and

the data to be deleted is data for which a delete command has been issued.

18. The control method of claim 10 , further comprising:

receiving the first information by the host device;

after receiving the first information, generating the second information based on the first information by the host device; and

transmitting the second information to the memory device by the host device.

Assignments (3)
CHANGE OF NAME AND ADDRESS Recorded Feb 4, 2022
From: K.K PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 058957/0124 →
CHANGE OF NAME AND ADDRESS Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058905/0582 →
MERGER Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: K.K PANGEA
Reel/Frame 058946/0675 →
Priority Claims (1)
JP 2015-038998 · Feb 27, 2015 · national
Continuity (3)
Continuation 14656506 · Mar 12, 2015
Provisional Application 62097532 · Dec 29, 2014
Related Publication 20180081799A1 · Mar 22, 2018