Disclosed is a successive-approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include a capacitor-resistor hybrid digital-to-analog converter (DAC), and apply a low-power switching method and an input signal range scaling method to the DAC, thereby significantly reducing surface area and power consumption.
1. A successive-approximation register (SAR) analog-to-digital converter (ADC) comprising:
a digital-to-analog converter (DAC),
wherein the DAC comprises:
a first capacitor array comprising a plurality of first capacitors;
a second capacitor array comprising a plurality of second capacitors; and
a resistor string suitable for generating differential reference voltages,
wherein the SAR ADC determines a digital code of high-order bits by selectively applying first and second reference voltages and an input signal to the first capacitors, and
wherein the SAR ADC determines a digital code of low-order bits by selectively applying the differential reference voltages and a common mode voltage to the second capacitors,
wherein when sampling the input signal, the SAR ADC applies the common mode voltage to top plates of the first and second capacitors, applies the input signal to bottom plates of the first capacitors, applies the common mode voltage to bottom plates of the capacitors corresponding to the least significant bits, and applies the input signal to bottom plates of capacitors corresponding to most significant bits among the second capacitors.
2. The SAR ADC of claim 1 ,
wherein the resistor string generates the differential reference voltages including levels which have a ratio of powers of 2, in the range of the first and second reference voltages, and
wherein the resistor string provides the differential reference voltages to capacitors corresponding to least significant bits among the second capacitors.
3. The SAR ADC of claim 1 ,
wherein capacities of the first capacitors have a ratio of powers of 2,
wherein each of the second capacitors is a unit capacitor, and
wherein the first capacitors and a part of the second capacitors are configured to sample the input signal.
4. The SAR ADC of claim 1 ,
wherein the first capacitor array comprises equally divided capacitor sets each including first and second equally divided capacitors having the same capacity, and
wherein the first and second equally divided capacitors are used for determining a digital code of most significant bits.
5. The SAR ADC of claim 4 , wherein the SAR ADC determines the digital code of the most significant bits by applying the first and second reference voltages to the first and second equally divided capacitors before an operation of a comparator, and by applying the first or second reference voltage to the first and second equally divided capacitors according to the comparison result after the operation of the comparator.
6. The SAR ADC of claim 5 ,
wherein the SAR ADC determines the digital code of high-order bits by selectively applying the first or second reference voltage to the first capacitors according to the comparison result of the comparator, and
wherein the SAR ADC determines the digital code of low-order bits by selectively applying the differential reference voltages to the second capacitors according to the comparison result of the comparator.
7. A successive-approximation register (SAR) analog-to-digital converter (ADC) comprising:
a digital-to-analog converter (DAC) comprising a first capacitor array including a plurality of first capacitors, a second capacitor array including a plurality of second capacitors, and a resistor string suitable for providing differential reference voltages;
a comparator suitable for comparing output signals of the DAC; and
a SAR logic circuit suitable for converting an input signal into a digital code using the comparison result,
wherein the SAR logic circuit determines a digital code of high-order bits by selectively applying first and second reference voltages and an input signal to the first capacitors, and
wherein the SAR logic circuit determines a digital code of low-order bits by selectively applying the differential reference voltages and a common mode voltage to the second capacitors,
wherein when the input signal is sampled, the SAR logic circuit applies the common mode voltage to top plates of the first and second capacitors, applies the input signal to bottom plates of the first capacitors, applies the common mode voltage to bottom plates of capacitors corresponding to least significant bits among the second capacitors, and applies the input signal to bottom plates of capacitors corresponding to most significant bits among the second capacitors.
8. The SAR ADC of claim 7 ,
wherein the resistor string comprises resistors coupled in series, and generates the differential reference voltages including levels which have a ratio of powers of 2, in the range of the first and second reference voltages,
wherein capacities of the first capacitors have a ratio of powers of 2, and
wherein each of the second capacitors is a unit capacitor.
9. The SAR ADC of claim 8 , wherein the first capacitors and a part of the second capacitors are configured to sample the input signal.
10. The SAR ADC of claim 7 ,
wherein the first capacitor array comprises equally divided capacitor sets each including first and second equally divided capacitors having the same capacity, and
wherein the SAR logic circuit determines a digital code of most significant bits by applying the first and second reference voltages to the first and second equally divided capacitors before the operation of the comparator, and by applying the first or second reference voltage to the first and second equally divided capacitors according to the comparison result of the comparator after the operation of the comparator.
11. The SAR ADC of claim 7 ,
wherein the SAR logic circuit determines the digital code of high-order bits by selectively applying the first and second reference voltages to the first capacitors according to the comparison result of the comparator, and
wherein the SAR logic circuit determines the digital code of low-order bits by selectively applying the differential reference voltages to the second capacitors according to the comparison result of the comparator.
12. The SAR ADC of claim 7 , further comprising a reference voltage generator for generating the first and second reference voltages.
13. A successive-approximation register (SAR) analog-to-digital converter (ADC) comprising:
a digital-to-analog converter (DAC),
wherein the DAC comprises:
a first capacitor array comprising first capacitors of which the capacities have a ratio of powers of 2;
a second capacitor array comprising a plurality of second capacitors each of which is a unit capacitor; and
a resistor string suitable for generating differential reference voltages including levels which have a ratio of powers of 2, in the range of first and second reference voltages,
wherein the first capacitors and a part of the second capacitors are configured to sample the input signal,
wherein when sampling the input signal, the SAR ADC applies the common mode voltage to top plates of the first and second capacitors, applies the input signal to bottom plates of the first capacitors, applies the common mode voltage to bottom plates of capacitors corresponding to least significant bits among the second capacitors, and applies the input signal to bottom plates of capacitors corresponding to most significant bits among the second capacitors.
14. The SAR ADC of claim 13 ,
wherein the first capacitor array comprises equally divided capacitor sets each including first and second equally divided capacitors having the same capacity, and
wherein the first and second equally divided capacitors are used for determining a digital code of the most significant bits.
15. The SAR ADC of claim 14 , wherein after the input signal is sampled, the SAR ADC blocks the common mode voltage from being applied to the top plates of the first and second capacitors, and determines the digital code of the most significant bits by applying the first and second reference voltages to the bottom plates of the first and second equally divided capacitors and applying the first or second reference voltage to the first and second equally divided capacitors according to a comparison result of a comparator.
16. The SAR ADC of claim 13 , wherein the SAR ADC determines the digital code of high-order bits by selectively applying the first and second reference voltages to the first capacitors, and determines the digital code of low-order bits by selectively applying the differential reference voltages to the second capacitors.
17. The SAR ADC of claim 13 , further comprising:
a comparator suitable for comparing output signals of the DAC; and
a SAR logic circuit suitable for converting the input signal into the digital code using the comparison result of the comparator.