Analog digital converter and method for analog to digital converting in the analog digital converter
An analog-to-digital converter is provided. An analog-to-digital converter includes a comparator including a first input node receiving an output of a plurality of first unit capacitors and a second input node receiving an output of a plurality of second unit capacitors, a control logic configured to output first and second control signals on the basis of an output signal of the comparator, and a reference voltage adjustment circuit configured to adjust an output voltage provided to the comparator on the basis of the first and second control signals. The reference voltage adjustment circuit comprises a first pull-up circuit configured to apply a first reference voltage to each of the plurality of first unit capacitors and a first pull-down circuit configured to apply a second reference voltage to each of the plurality of second unit capacitors, based on v.
1. An analog-to-digital converter comprising:
a comparator including a first input node receiving an output of a plurality of first unit capacitors and a second input node receiving an output of a plurality of second unit capacitors;
a control logic configured to output first and second control signals on the basis of an output signal of the comparator; and
a reference voltage adjustment circuit configured to adjust an output voltage provided to the comparator on the basis of the first and second control signals, wherein the reference voltage adjustment circuit comprises a first pull-up circuit configured to apply a first reference voltage to each of the plurality of first unit capacitors and a first pull-down circuit configured to apply a second reference voltage to each of the plurality of second unit capacitors, based on the first and second controls signals.
2. The analog-to-digital converter of claim 1 , wherein the first pull-up circuit comprises a first sampling switch configured to receive a first input signal, first and second reference voltage switches configured to receive the first control signal and apply first and second reference voltages, and a first successive-approximation-register (SAR) operation switch disposed between the first and second reference voltage switches.
3. The analog-to-digital converter of claim 2 , wherein when a sampling operation is performed, the first sampling switch is turned on by receiving a first sampling operation clock signal, the first SAR operation switch is turned off by receiving a first SAR clock signal, and the first reference voltage switch is turned off by receiving the first control signal such that the first input signal is sampled in a first unit capacitor of the first pull-up circuit.
4. The analog-to-digital converter of claim 3 , wherein the first pull-down circuit comprises a second sampling switch configured to receive a second input signal, third and fourth reference voltage switches configured to receive the second control signal and apply first and second reference voltages, and a second SAR operation switch disposed between the third and fourth reference voltage switches.
5. The analog-to-digital converter of claim 4 , wherein when a sampling operation is performed, the second sampling switch is turned on by receiving a second sampling operation clock signal, the second SAR operation switch is turned off by receiving a second SAR clock signal, and the fourth reference voltage switch is turned off by receiving the second control signal such that the second input signal is sampled in a second unit capacitor of the first pull-down circuit.
6. The analog-to-digital converter of claim 4 , wherein when a conversion operation is performed, the second sampling switch is turned off, the second SAR operation switch is turned on by receiving a second SAR operation clock signal, and one of the third and fourth reference voltage switches is turned on by receiving the second control signal such that the second reference voltage is applied to a second unit capacitor of the first pull-down circuit.
7. The analog-to-digital converter of claim 2 , wherein when a conversion operation is performed, the first sampling switch is turned off, the first SAR operation switch is turned on by receiving a first SAR operation clock signal, and one of the first and second reference voltage switches is turned on by receiving the first control signal such that the first reference voltage is applied to a first unit capacitor of the first pull-up circuit.
8. The analog-to-digital converter of claim 1 , wherein neither of the first and second reference voltages is applied while a first input signal is being input to a first unit capacitor of the first pull-up circuit, and only one of the first and second reference voltages is applied while the first input signal is being input to the first unit capacitor.
9. The analog-to-digital converter of claim 8 , wherein neither of the first and second reference voltages is applied while a second input signal is being input to a second unit capacitor of the first pull-down circuit, and only one of the first and second reference voltages is applied while the second input signal is being input to the second unit capacitor.
10. The analog-to-digital converter of claim 1 , wherein the first pull-up circuit and the first pull-down circuit provide a first output voltage to the comparator, and the first pull-up circuit and the first pull-down circuit are alternately disposed.
11. The analog-to-digital converter of claim 10 , wherein the reference voltage adjustment circuit further comprises a second pull-up circuit and a second pull-down circuit that provide a second output voltage, which is equal in magnitude but opposite in sign to the first output voltage, to the comparator, and the second pull-up circuit and the second pull-down circuit are alternately disposed.
12. The analog-to-digital converter of claim 1 , wherein the reference voltage adjustment circuit comprises a first capacitor array including a plurality of binary-weighted unit capacitors and a second capacitor array including a plurality of thermometer code-based unit capacitors.
13. An analog-to-digital converter comprising:
a first capacitor array including a plurality of thermometer code-based first unit capacitors used to determine upper bits of a digital output signal corresponding to an analog input signal;
a second capacitor array including a plurality of binary-weighted second unit capacitors used to determine lower bits of the digital output signal; and
a control logic configured to receive a reference voltage from the first and second capacitor arrays to output first and second control signals,
wherein the first and second capacitor arrays comprise first and second operation switches configured to apply first and second reference voltages on the basis of the first and second control signals, respectively.
14. The analog-to-digital converter of claim 13 , wherein the first operation switch comprises a first sampling switch configured to receive a first input signal, first and second reference voltage switches configured to receive the first control signal and apply first and second reference voltages, and a first successive-approximation-register (SAR) operation switch disposed between the first and second reference voltage switches, and
when a sampling operation is performed, the first sampling switch is turned on by receiving a first sampling operation clock signal, the first SAR operation switch is turned off by receiving a first SAR clock signal, and the first reference voltage switch is turned off by receiving the first control signal such that the first input signal is sampled in a first unit capacitor connected to the first operation switch.
15. The analog-to-digital converter of claim 14 , wherein when a conversion operation is performed, the first sampling switch is turned off, the first SAR operation switch is turned on by receiving a first SAR operation clock signal, and one of the first and second reference voltage switches is turned on by receiving the first control signal such that the first reference voltage is applied to a first unit capacitor connected to the first operation switch.
16. The analog-to-digital converter of claim 13 , wherein the second operation switch comprises a second sampling switch configured to receive a second input signal, third and fourth reference voltage switches configured to receive the second control signal and apply first and second reference voltages, and a second SAR operation switch disposed between the third and fourth reference voltage switches, and when a sampling operation is performed, the second sampling switch is turned on by receiving a second sampling operation clock signal, the second SAR operation switch is turned off by receiving a second SAR clock signal, and the fourth reference voltage switch is turned off by receiving the second control signal such that the second input signal is sampled in a second unit capacitor connected to the second operation switch.
17. The analog-to-digital converter of claim 16 , wherein when a conversion operation is performed, the second sampling switch is turned off, the second SAR operation switch is turned on by receiving a second SAR operation clock signal, and one of the third and fourth reference voltage switches is turned on by receiving the second control signal such that the second reference voltage is applied to a second unit capacitor connected to the second operation switch.
18. The analog-to-digital converter of claim 13 , wherein each operation switch comprises a pair of switches configured to receive a corresponding one of the control signals and apply the first and second reference voltages, and a switch disposed between the pair that is controlled by a clock signal.
19. A method of performing analog-to-digital conversion using an analog-to-digital converter including a comparator including a plurality of nodes to which outputs of a plurality of first unit capacitors and outputs of a plurality of second unit capacitors are connected, a control logic, a pull-up circuit and a pull-down circuit, the method comprising:
outputting, by the control logic, first and second control signals on the basis of an output signal of the comparator; and adjusting, by the pull-up circuit and the pull-down circuit a reference voltage applied to the plurality of first unit capacitors and the plurality of second unit capacitors on the basis of the first and second control signals,
wherein the adjusting comprises the pull-up circuit applying a first reference voltage to each of the plurality of first unit capacitors, and the pull-down circuit applying a second reference voltage to each of the plurality of second unit capacitors that is different from the first reference voltage.
20. The conversion method of claim 19 , wherein the pull-up circuit comprises a first sampling switch configured to receive a first input signal, first and second reference voltage switches configured to receive the first control signal and apply first and second reference voltages, and a first successive-approximation-register (SAR) operation switch disposed between the first and second reference voltage switches, and when a sampling operation is performed, the first sampling switch is turned on by receiving a first sampling operation clock signal, the first SAR operation switch is turned off by receiving a first SAR clock signal, and the first reference voltage switch is turned off by receiving the first control signal such that the first input signal is sampled in each of the plurality of first unit capacitors, and when a conversion operation is performed, the first sampling switch is turned off, the first SAR operation switch is turned on by receiving a first SAR operation clock signal, and one of the first and second reference voltage switches is turned on by receiving the first control signal such that the first reference voltage is applied to each of the plurality of first unit capacitors.
21. The conversion method of claim 20 , wherein the pull-down circuit comprises a second sampling switch configured to receive a second input signal, third and fourth reference voltage switches configured to receive the second control signal and apply first and second reference voltages, and a second SAR operation switch disposed between the third and fourth reference voltage switches, when a sampling operation is performed, the second sampling switch is turned on by receiving a second sampling operation clock signal, the second SAR operation switch is turned off by receiving a second SAR clock signal, and the fourth reference voltage switch is turned off by receiving the second control signal such that the second input signal is sampled in each of the plurality of second unit capacitors, and when a conversion operation is performed, the second sampling switch is turned off, the second SAR operation switch is turned on by receiving a second SAR operation clock signal, and one of the third and fourth reference voltage switches is turned on by receiving the second control signal such that the second reference voltage is applied to each of the plurality of second unit capacitors.