Buried contact to provide reduced VFET feature-to-feature tolerance requirements
Embodiments are directed to a semiconductor device. The semiconductor device includes a first semiconductor fin formed opposite a surface of a first active region of a substrate. The semiconductor device further includes a second semiconductor fin formed opposite a surface of a second active region of the substrate. The semiconductor device further includes a self-aligned buried contact formed over portions of the first active region and the second active region and between the first semiconductor fin and the second semiconductor fin.
1. A method of forming a semiconductor device, the method comprising:
forming a first semiconductor fin opposite a surface of a first active region of a substrate, the first active region comprising a first dopant type;
forming a second semiconductor fin opposite a surface of a second active region of the substrate, the second active region comprising a second dopant type complementary to the first dopant type;
forming a first gate over the first active region of the substrate, the first gate on a sidewall of the first semiconductor fin;
forming a second gate over the second active region of the substrate, the second gate on a sidewall of the second semiconductor fin;
forming a self-aligned buried contact over portions of the first active region and the second active region and between the first semiconductor fin and the second semiconductor fin;
forming a dielectric layer over portions of the self-aligned buried contact, the dielectric layer comprising a first dielectric material on a surface of the first gate;
forming a spacer between the first gate and the self-aligned buried contact, the spacer comprising a spacer material having an etch selectivity relative to the first dielectric material; and
forming a contact in the dielectric layer, a bottommost surface of the contact positioned in direct contact with a topmost surface of the self-aligned buried contact and a topmost surface of the first gate.
2. The method of claim 1 , wherein forming the first gate comprises depositing a gate metal over the surface of the first active region and the surface of the second active region.
3. The method of claim 2 , wherein forming the dielectric layer further comprises depositing the first dielectric material opposite a surface of the gate metal.
4. The method of claim 3 , further comprising etching a portion of the gate metal to form the first gate over a channel region of the first semiconductor fin and a second gate over a channel region of the second semiconductor fin.
5. The method of claim 4 , wherein forming the self-aligned buried contact further comprises forming the spacer on a sidewall of the first gate.
6. The method of claim 5 , wherein forming the self-aligned buried contact further comprises recessing a portion of the first active region of the substrate and a portion of the second active region of the substrate.
7. The method of claim 5 , wherein the spacer has a thickness of about 5 nanometers to about 12 nanometers.