Fully molded miniaturized semiconductor module
A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imagable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT).
1. A semiconductor module, comprising:
a fully molded base portion comprising:
a planar surface,
a semiconductor die disposed within the fully molded base portion, the semiconductor die comprising an active surface comprising contact pads,
conductive pillars coupled to the contact pads and the conductive pillars extending to the planar surface, and
an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion;
a build-up interconnect structure comprising a conductive via, the build-up interconnect structure being contained within a footprint of the fully molded base portion, a position or alignment of the conductive via being adjusted by unit specific patterning to account for shift of the semiconductor die;
surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars; and
a SMD component electrically coupled to the SMD land pads with surface mount technology (SMT).
2. The semiconductor module of claim 1 , wherein the SMD component comprises at least one of a semiconductor die, a wafer level chip scale package (WLCSP), an integrated circuit (IC), a surface mount device, an active device, or a passive device or a solderable passive such as a resistor or a capacitor.
3. The semiconductor module of claim 1 , wherein the SMD component being electrically coupled to the SMD land pads further comprises:
the SMD component comprising solderable terminations;
solder paste disposed over the SMD land pads; and
the solderable terminations being disposed over, and electrically coupled to, the SMD land pads while the solderable terminations are in contact with the solder paste.
4. The semiconductor module of claim 3 , wherein SMD land pads comprise a solderable surface finish of: nickel (Ni) and gold (Au); Ni, palladium (Pd) and Au; tin (Sn); solder; or Organic Solderability Preservative (OSP).
5. The semiconductor module of claim 1 , wherein the SMD component is coupled to the land pads with solder bumps.
6. The semiconductor module of claim 1 , wherein the build-up interconnect structure comprises high-density multilayer routing layers.
7. The semiconductor module of claim 1 , wherein:
the SMD component is partially within a footprint of the semiconductor die and partially without a footprint of the semiconductor die; and
at least one of the SMD land pads is positioned over an edge of the footprint of the semiconductor die within the fully molded structure.
8. The semiconductor module of claim 1 , further comprising:
a first output connector of the module adapted to be coupled to a battery; and
a second connector of the module adapted to be coupled to a display.
9. The semiconductor module of claim 1 , wherein a second encapsulant material is disposed over and around the SMD component to form a fully molded top portion.
10. A semiconductor module, comprising:
a fully molded base portion comprising a planar surface that further comprises:
a semiconductor die disposed within the fully molded base portion, the semiconductor die comprising contact pads,
conductive pillars coupled to the contact pads and extending to the planar surface, and
an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion;
a build-up interconnect structure comprising a routing layer disposed over the fully molded base portion;
at least one SMD component (SMD) electrically coupled to the routing layer, wherein the SMD component comprises one or more of a semiconductor die, a wafer level chip scale package (WLCSP), an integrated circuit (IC), a surface mount device, an active device, or a passive device or a solderable passive such as a resistor or a capacitor; and
a second encapsulant material disposed over and around the SMD component to form a fully molded top portion.
11. The semiconductor module of claim 10 , wherein the SMD component being electrically coupled to the routing layer further comprises:
the SMD component comprising solderable terminations;
solder paste disposed over the routing layer; and
the solderable terminations being disposed over, and electrically coupled to, the routing layer when the solderable terminations are in contact with the solder paste.
12. The semiconductor module of claim 10 , wherein the IC component is coupled to the routing layer with solder bumps.
13. The semiconductor module of claim 10 , wherein:
the SMD component is partially within a footprint of the semiconductor die and partially without a footprint of the semiconductor die.
14. The semiconductor module of claim 10 , further comprising a shielding layer disposed over the encapsulant material of the fully molded base portion and the second encapsulant material of the fully molded top portion, the shielding layer being coupled to build-up interconnect structure.
15. The semiconductor module of claim 10 , wherein the encapsulant material of the fully molded base portion is of a same material as the second encapsulant of the fully molded top portion.
16. A method of making a semiconductor module, comprising:
forming electrical interconnects on a semiconductor die;
encapsulating the semiconductor die with an encapsulant to form a first embedded portion with the electrical interconnects exposed from the encapsulant;
forming a build-up interconnect structure comprising a conductive RDL layer over the first embedded portion after encapsulating the semiconductor die, the build-up interconnect structure being electrically connected to the electrical interconnects, a position or alignment of a portion of the build-up interconnect structure being adjusted by unit specific patterning;
forming surface mount device (SMD) land pads electrically coupled to the conductive RDL layer; and
coupling a SMD component to the SMD land pads with surface mount technology (SMT) to provide an electrical connection between the SMD component and the semiconductor die through the conductive pillars and the build-up interconnect structure.
17. The method of claim 16 further comprising forming the build-up interconnect structure comprising the conductive RDL routing layer being adjusted by unit specific patterning to account for shift of the semiconductor die within the first embedded portion.
18. The method of claim 16 , wherein the SMD component comprises a semiconductor die, a wafer level chip scale package (WLCSP), an integrated circuit (IC), a surface mount device, an active device, or a passive device or a solderable passive such as a resistor or a capacitor.
19. The method of claim 16 , further comprising electrically testing the semiconductor die within the first embedded portion before coupling any of the SMD components to the first embedded portion.
20. The method of claim 16 , further comprising coupling the SMD component to the SMD land pads so that the SMD component is partially within a footprint of the semiconductor die and partially without a footprint of the semiconductor die.