IP Library Granted Patent US 10,205,075
Granted Patent B2
US 10,205,075 · App. 15/826,048 · Granted Feb 12, 2019

Semiconductor light emitting device including cap structure and method of making same

Inventors: Anusha Pokhriyal (Sunnyvale, CA); Mariana Munteanu (Sunnyvale, CA); Fariba Danesh (Pleasanton, CA)
Assignee: GLO AB
H01L33/62H01L24/27H01L24/29H01L33/007H01L33/06H01L33/10H01L33/12H01L33/20H01L33/32H01L33/38H01L33/405H01L33/44H01L33/60H01L2224/29083H01L2224/29109H01L2224/29111H01L2224/29139H01L2224/29144H01L2224/29147H01L2224/29155H01L2224/29166H01L2224/29169H01L2224/29171H01L2224/29184H01L2924/014H01L2924/12041H01L2933/0016H01L2933/0025H01L2933/0058H01L2933/0066
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Quick Facts
Patent No.
US 10,205,075
App. No.
15/826,048
Granted
Feb 12, 2019
Kind
B2
Abstract

A light emitting device and method of forming the same, the light emitting device including: a substrate, a buffer layer disposed on the substrate, a semiconductor mesa disposed on the buffer layer and including a first semiconductor layer, a light emitting active layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the first semiconductor layer, a contact layer disposed on an upper surface of the mesa, a passivation layer covering sidewalls of the mesa and the contact layer, and a cap structure including a reflective layer covering an upper surface of the contact layer, and a solder layer including a recess in which the reflective layer is disposed.

Claims (26)

1. A light emitting device comprising:

a substrate;

a buffer layer disposed on the substrate;

a semiconductor mesa disposed on the buffer layer and comprising a first semiconductor layer, a light emitting active layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the first semiconductor layer;

a contact layer disposed on an upper surface of the mesa;

a passivation layer covering sidewalls of the mesa and the contact layer; and

a cap structure comprising a reflective layer covering an upper surface of the contact layer, and a solder layer comprising a recess in which the reflective layer is disposed.

2. The device of claim 1 , wherein the cap structure further comprises an adhesion layer disposed between the contact layer and the reflective layer.

3. The device of claim 2 , wherein the adhesion layer comprises Ni, Ti, Pt, TiW, or Cr.

4. The device of claim 2 , wherein the adhesion layer has a thickness ranging from about 10 angstroms to about 5000 angstroms.

5. The device of claim 1 , wherein the cap structure further comprises an adhesion layer disposed between the reflective layer and the solder layer.

6. The device of claim 5 , wherein the adhesion layer comprises Ni, Ti, Pt, TiW, or Cr.

7. The device of claim 5 , wherein the adhesion layer has a thickness ranging from about 10 angstroms to about 5000 angstroms.

8. The device of claim 1 , wherein the cap structure further comprises a wetting layer disposed between the reflective layer and the solder layer.

9. The device of claim 8 , wherein the wetting layer comprises Ni, TiW, Pt, Au, Ag, or Cr.

10. The device of claim 1 , wherein the solder layer comprises Sn, SnAu, SnAg, SnCu, SnAgCu, SnIn, SnNi, or SnAuNi.

11. The device of claim 1 , wherein the reflective layer and the solder layer cover sidewalls of the second semiconductor layer and the active layer.

12. The device of claim 1 , wherein the passivation layer is disposed between the reflective layer and the sidewalls of the second semiconductor layer and the active layer.

13. The device of claim 1 , wherein the reflective layer comprises Al, Ag, Au, or any combination thereof.

14. The device of claim 13 , wherein the reflective layer has a thickness ranging from about 500 angstroms to about 5000 angstroms.

15. The device of claim 1 , wherein the cap structure comprises:

a first adhesion layer disposed between the contact layer and the reflective layer;

a second adhesion layer disposed between the reflective layer and the solder layer; and

a wetting layer disposed between the second adhesion layer and the solder layer.

16. The device of claim 1 , wherein the device comprises a recess at least partially defined by sidewalls of the first semiconductor layer and a lower surface of the cap structure.

17. The device of claim 1 , wherein the passivation layer covers edges of the upper surface of the contact layer.

Assignments (10)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2024
From: GLO TECHNOLOGIES LLC
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 068297/0220 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 6, 2023
From: SYSONAN, INC.
To: GLO TECHNOLOGIES LLC
Reel/Frame 065178/0210 →
CHANGE OF NAME Recorded Oct 5, 2023
From: NANOSYS, INC.
To: SYSONAN, INC.
Reel/Frame 065156/0416 →
TERMINATION AND RELEASE OF PATENT SECURITY AGREEMENT RECORDED AT REEL 059569 / FRAME 0840 Recorded Sep 7, 2023
From: FORTRESS CREDIT CORP.,
To: NANOSYS, INC.
Reel/Frame 064836/0263 →
SECURITY INTEREST Recorded Apr 1, 2022
From: NANOSYS, INC.
To: FORTRESS CREDIT CORP., AS AGENT
Reel/Frame 059569/0840 →
NUNC PRO TUNC ASSIGNMENT Recorded Aug 13, 2021
From: GLO AB
To: NANOSYS, INC.
Reel/Frame 057184/0564 →
RELEASE OF SECURITY INTEREST Recorded Apr 12, 2021
From: HERCULES CAPITAL, INC.
To: GLO AB
Reel/Frame 057210/0690 →
SECURITY INTEREST Recorded Jan 23, 2019
From: GLO AB
To: HERCULES CAPITAL INC.
Reel/Frame 048110/0063 →
ASSIGNMENT OF IP SECURITY AGREEMENT Recorded Dec 12, 2018
From: GLO AB
To: HERCULES CAPITAL, INC., AS ADMINISTRATIVE AGENT
Reel/Frame 049042/0527 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2018
From: POKHRIYAL, ANUSHA; MUNTEANU, MARIANA; DANESH, FARIBA
To: GLO AB
Reel/Frame 047089/0666 →
Continuity (2)
Provisional Application 62428799 · Dec 1, 2016
Related Publication 20180159005A1 · Jun 7, 2018