Display driver semiconductor device and manufacturing method thereof
A display driver semiconductor device includes a high voltage well region being formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer. The first insulating layer may be formed using a chemical vapor deposition (CVD) process and the second insulating layer is formed using a thermal oxide process.
1. A method for manufacturing a semiconductor device, the method comprising:
forming trench isolating regions on a substrate;
forming a well region on the substrate;
forming drift regions in the well region;
forming a gate insulating layer overlapped with the drift regions;
forming a gate electrode on the gate insulating layer;
forming spacers on side walls of the gate electrode;
forming a source region and a drain region in the drift regions;
forming a first insulating layer on the substrate and the gate electrode;
forming a second insulating layer on the first insulating layer; and
forming a contact plug in the first insulating layer and the second insulating layer.
2. The method for manufacturing the semiconductor device of claim 1 , wherein the gate insulating layer comprises a first gate insulating layer and a second gate insulating layer, the first gate insulating layer being a CVD insulating layer and the second gate insulating layer being a thermal oxide layer.
3. The method for manufacturing the semiconductor device of claim 1 , wherein the source and drain regions are formed at a predetermined distance from the spacers.
4. The method for manufacturing the semiconductor device of claim 1 , further comprising:
forming a silicide blocking insulating layer on the substrate to extend to the spacers and an edge of the gate electrode.
5. The method for manufacturing the semiconductor device of claim 1 , further comprising:
forming a dummy gate electrode on the trench isolating regions.
6. The semiconductor device of claim 1 , wherein the first insulating layer comprises a silicon nitride or a silicon oxynitride.
7. A semiconductor device, comprising:
a thick gate insulating layer on a substrate;
a source region and a drain region formed in the substrate;
a first drift region and a second drift region surrounding the source region and the drain region, respectively;
a gate electrode on the thick gate insulation layer;
spacers formed on side walls of the gate electrode;
a silicide blocking insulating layer formed on the spacers;
a first insulating layer formed on the silicide blocking insulating layer;
a second insulating layer formed on the first insulating layer; and
a first contact plug and a second contact plug connected with the source and drain regions, respectively, in the first and second insulating layers.
8. The semiconductor device of claim 7 , wherein the thick gate insulating layer comprises a first gate insulating layer and a second gate insulating layer, the first gate insulating layer being a chemical vapor deposition (CVD) insulating layer and the second gate insulating layer being a thermal oxide layer.
9. The semiconductor device of claim 7 , wherein the silicide blocking insulating layer is formed extended to an edge of the gate electrode.
10. The semiconductor device of claim 7 , wherein the source and drain regions are formed at a predetermined distance from the spacers.
11. The semiconductor device of claim 7 , wherein the first insulating layer comprises a silicon nitride or a silicon oxynitride.
12. A semiconductor device, comprising:
a source region and a drain region in a substrate;
a thick gate insulating layer on the substrate;
a gate electrode on the thick gate insulation layer;
spacers formed on side walls of the gate electrode;
a silicide blocking insulating layer selectively formed on the substrate;
a thin insulating layer formed on the silicide blocking insulating layer;
an interlayer insulating layer formed on the thin insulating layer; and
a contact plug formed in the interlayer insulating layer,
wherein the silicide blocking insulating layer is formed over the side walls and a partial region of respective top surfaces of the source region, the drain region, and the gate electrode.
13. The semiconductor device of claim 12 , wherein the source and drain regions are formed at a predetermined distance from the spacers.
14. The semiconductor device of claim 12 , further comprising a trench isolating region and a drift region formed in the substrate,
wherein the trench isolating region has a maximum depth larger than a maximum depth of the drift region which is larger than a maximum depth of the source or drain region, the respective maximum depths being measured from an upper surface of the substrate.
15. The semiconductor device of claim 14 , wherein the source region or the drain region is disposed in the drift region.
16. The semiconductor device of claim 12 , wherein an edge portion of the gate electrode has a height greater than a height of a center portion of the gate electrode.
17. The semiconductor device of claim 12 , further comprising a silicide layer formed on the gate electrode,
wherein the silicide layer has a length smaller than a length of the gate electrode.