FAN-OUT SEMICONDUCTOR PACKAGE AND PACKAGE SUBSTRATE COMPRISING THE SAME
A fan-out semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the inactive surface of the semiconductor chip; a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip; a reinforcing plate disposed on the encapsulant and having a first surface facing the inactive surface of the semiconductor chip and a second surface opposing the first surface; and rigid patterns formed on at least one of the first surface and the second surface of the reinforcing plate.
1 . A fan-out semiconductor package comprising:
a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the inactive surface of the semiconductor chip;
a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip;
a reinforcing plate disposed on the encapsulant and having a first surface facing the inactive surface of the semiconductor chip and a second surface opposing the first surface; and
rigid patterns disposed on at least one of the first surface and the second surface of the reinforcing plate.
2 . The fan-out semiconductor package of claim 1 , wherein the reinforcing plate has an elastic modulus greater than that of the encapsulant.
3 . The fan-out semiconductor package of claim 1 , wherein the reinforcing plate includes a glass fiber, an inorganic filler, and an insulating resin.
4 . The fan-out semiconductor package of claim 3 , further comprising a resin layer disposed on the second surface of the reinforcing plate,
wherein the resin layer includes an inorganic filler and an insulating resin.
5 . The fan-out semiconductor package of claim 1 , wherein the rigid patterns include a metal or an organic material.
6 . The fan-out semiconductor package of claim 1 , wherein the rigid patterns are formed in only a fan-in region or a fan-out region.
7 . The fan-out semiconductor package of claim 1 , wherein the rigid patterns are formed on the first surface of the reinforcing plate, and are embedded in the encapsulant.
8 . The fan-out semiconductor package of claim 1 , further comprising a resin layer disposed on the second surface of the reinforcing plate,
wherein the rigid patterns are formed on the second surface of the reinforcing plate, and are embedded in the resin layer.
9 . The fan-out semiconductor package of claim 1 , further comprising a support member having a through-hole,
wherein the semiconductor chip is disposed in the through-hole.
10 . The fan-out semiconductor package of claim 9 , wherein the support member includes a first insulating layer, a first redistribution layer in contact with the connection member and embedded in a first surface of the first insulating layer, and a second redistribution layer disposed on a second surface of the first insulating layer opposing the first surface of the first insulating layer, and
the first and second redistribution layers are electrically connected to the connection pads.
11 . The fan-out semiconductor package of claim 10 , wherein the support member further includes a second insulating layer disposed on the first insulating layer and covering the second redistribution layer and a third redistribution layer disposed on the second insulating layer, and
the third redistribution layer is electrically connected to the connection pads.
12 . The fan-out semiconductor package of claim 10 , wherein a distance between the redistribution layer of the connection member and the first redistribution layer is greater than that between the redistribution layer of the connection member and the connection pad.
13 . The fan-out semiconductor package of claim 9 , wherein the support member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on opposite surfaces of the first insulating layer, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer, and
the first to third redistribution layers are electrically connected to the connection pads.
14 . The fan-out semiconductor package of claim 13 , wherein the support member further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer and a fourth redistribution layer disposed on the third insulating layer, and
the fourth redistribution layer is electrically connected to the connection pads.
15 . The fan-out semiconductor package of claim 13 , wherein the first insulating layer has a thickness greater than that of the second insulating layer.
16 . A fan-out semiconductor package comprising:
a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the inactive surface of the semiconductor chip;
a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip; and
a reinforcing plate disposed on the encapsulant and having a first surface facing the inactive surface of the semiconductor chip and a second surface opposing the first surface,
wherein the reinforcing plate has a coefficient of thermal expansion smaller than that of the encapsulant.
17 . The fan-out semiconductor package of claim 16 , further comprising rigid patterns disposed on at least one of the first surface and the second surface of the reinforcing plate.
18 . The fan-out semiconductor package of claim 16 , wherein the reinforcing plate has an elastic modulus greater than that of the encapsulant.
19 . A package substrate comprising:
a plurality of unit packages each including a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, an encapsulant encapsulating at least portions of the inactive surface of the semiconductor chip, a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip, a reinforcing plate disposed on the encapsulant and having a first surface facing the inactive surface of the semiconductor chip and a second surface opposing the first surface, and rigid patterns formed on at least one of the first surface and the second surface of the reinforcing plate.
20 . The package substrate of claim 19 , wherein a larger number of rigid patterns are formed in unit packages, among the plurality of unit packages, in which unit warpage is relatively high, than in unit packages, among the plurality of unit packages, in which unit warpage is relatively low.