FinFET SRAM layout and method of making the same
A method of forming a finFET SRAM and related device, are provided. Embodiments include forming a plurality of silicon fins in a substrate; and forming a gate over each of the fins, wherein all of the fins are diagonally skewed in a single direction relative to the gates, and all of the gates extend in a single direction relative to the respective fins.
1. A method comprising:
forming a plurality of silicon fins in a substrate;
forming a gate over each of the fins; and
forming source/drain (S/D) contacts in a diagonally skewed direction relative to the gates; and
wherein all of the fins are diagonally skewed in a single direction relative to the gates, and
wherein all of the gates extend in a single direction relative to the respective fins.
2. The method according to claim 1 , comprising:
forming the fins and gates as a fin field effect transistor (finFET) memory device.
3. The method according to claim 2 , wherein the finFET memory device comprises static random-access memory (SRAM) cell.
4. The method according to claim 3 , wherein the SRAM cell comprises a six transistor finFET SRAM high density (HD) cell.
5. The method according to claim 1 , wherein the single direction of the fins is non-orthogonal relative to the respective gates.
6. The method according to claim 1 , wherein the single direction of the gates is non-orthogonal relative to the respective fins.
7. The method according to claim 1 , comprising:
forming each fin at an angle of 50 to 70 degrees relative to the respective gate.
8. The method according to claim 7 , comprising:
forming each fin at an angle of 66 degrees relative to the respective gate.
9. A device comprising:
a plurality of silicon fins formed in a substrate; and
a gate formed over each of the fins,
wherein all of the fins are diagonally skewed in a single direction relative to the gates, and
wherein all of the gates extend in a single direction relative to the respective fins, and
wherein the finFET memory device comprises static random-access memory (SRAM) cell.
10. The device according to claim 9 , comprising:
the fins and gates formed as a fin field effect transistor (finFET) memory device.
11. The device according to claim 9 , wherein the SRAM cell comprises a six transistor finFET SRAM high density (HD) cell.
12. The device according to claim 9 , wherein the single direction of the fins is non-orthogonal relative to the respective gates.
13. The device according to claim 9 , wherein the single direction of the gates is non-orthogonal relative to the respective fins.
14. The device according to claim 9 , comprising:
each fin formed at an angle of 50 to 70 degrees relative to the respective gate.
15. The device according to claim 14 , comprising:
each fin formed at an angle of 66 degrees relative to the respective gate.
16. The device according to claim 9 , further comprising:
source/drain (S/D) contacts formed in a diagonally skewed direction relative to the gates.
17. A method comprising:
forming a plurality of silicon fins in a substrate; and
forming a gate over each of the fins,
wherein all of the fins are diagonally skewed in a single direction at an angle relative to the gates,
wherein all of the gates extend in a single direction relative to the respective fins, and
the fins and gates comprise a six transistor finFET SRAM high density (HD) cell.
18. The method according to claim 17 , comprising:
forming each fin at an angle of 66 degrees relative to the respective gate.