Semiconductor integrated circuit adapted to output pass/fail results of internal operations
In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
1. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells;
a latch circuit configured to latch data read from at least one of the memory cells; and
a cache circuit configured to hold data transferred from the latch circuit, wherein
after the semiconductor memory device receives a first command, an address, a second command, and a third command, an operation of outputting first data to an outside of the semiconductor memory device from the cache circuit is executable in parallel with and concurrently with an operation of reading second data from the memory cell by the latch circuit.
2. The semiconductor memory device according to claim 1 , wherein
the semiconductor memory device concurrently outputs first and second information to the outside of the semiconductor memory device in a status read operation,
the first information is true ready/busy information, and
the second information is cache ready/busy information.
3. The semiconductor memory device according to claim 1 , wherein
the first data and the second data are read from an identical block, and
memory cells included in the block are concurrently erasable.
4. The semiconductor memory device according to claim 2 , wherein
the semiconductor memory device outputs the first information from a first I/O pad to the outside of the semiconductor memory device, and outputs the second information from a second I/O pad to the outside of the semiconductor memory device.
5. The semiconductor memory device according to claim 1 , wherein
after the semiconductor memory device receives another third command, an operation of outputting, by the cache circuit, the second data to the outside of the semiconductor memory device is executable in parallel with and concurrently with an operation of reading third data from the memory cell by the latch circuit.
6. The semiconductor memory device according to claim 1 , wherein the latch circuit includes two inverters.
7. The semiconductor memory device according to claim 6 , wherein the cache circuit includes two inverters.
8. The semiconductor memory device according to claim 1 , further comprising an output circuit coupled to the latch circuit via the cache circuit.
9. The semiconductor memory device according to claim 8 , wherein
the output circuit is coupled to an I/O pad, and
the semiconductor memory device outputs the first data to the outside of the semiconductor memory device from the I/O pad.
10. The semiconductor memory device according to claim 8 , wherein the cache circuit is coupled between a bit line and the output circuit.
11. The semiconductor memory device according to claim 1 , further comprising two bit lines, wherein
the latch circuit is coupled to the two bit lines, and
one of the two bit lines is selected and the other bit line is non-selected when the latch circuit is in operation.
12. The semiconductor memory device according to claim 1 , further comprising two bit lines, wherein
the latch circuit is coupled to the two bit lines,
one of the two bit lines is selected and the other bit line is not selected when the latch circuit is in operation, and
the one of the bit lines is coupled to memory cells connected in series in the memory cell array.
13. The semiconductor memory device according to claim 1 , further comprising two transistors provided between the latch circuit and the cache circuit.
14. The semiconductor memory device according to claim 1 , further comprising:
a plurality of latch circuits include the latch circuit; and
a plurality of cache circuits include the cache circuit, wherein
the latch circuits and the cache circuits are identical in number.
15. The semiconductor memory device according to claim 1 , further comprising another memory cell array including a plurality of memory cells, wherein
a half of a block is arranged in the memory cell array and another half of the block is arranged in said another memory cell array, and
memory cells in the block are concurrently erasable.
16. The semiconductor memory device according to claim 1 , further comprising another memory cell array including a plurality of memory cells, wherein
a block is arranged in the memory cell array or in said another memory cell array, and
memory cells in the block are concurrently erasable.
17. The semiconductor memory device according to claim 1 , further comprising:
another memory cell array including a plurality of memory cells; and
two row decoders provided between the memory cell array and said another memory cell array, wherein
one of the row decoders is coupled to the memory cells, and
another row decoder is coupled to said another memory cell array.
18. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells;
a cache circuit configured to hold data input from an I/O pad; and
a latch circuit configured to latch data transferred from the cache circuit and transfer the latched data to at least one of the memory cells, wherein
after the semiconductor memory device receives a first command, a first address, first data, a second command, a third command, a second address, second data, and a fourth command, an operation of inputting the second data to the cache circuit is executable in parallel with and concurrently with an operation of applying a voltage to write the first data to the memory cell in a write operation,
the third command is the same as the first command,
the fourth command is different from the second command,
the semiconductor memory device concurrently outputs first and second information from the I/O pad in a status read operation,
the first information is true ready/busy information, and
the second information is cache ready/busy information.
19. The semiconductor memory device according to claim 18 , wherein
the first and second data are transferred to an identical block, and
memory cells included in the block are concurrently erasable.
20. The semiconductor memory device according to claim 18 , further comprising two bit lines, wherein
the latch circuit is coupled to the two bit lines, and
one of the two bit lines is selected and the other bit line is non-selected when the latch circuit is in operation.
21. The semiconductor memory device according to claim 18 , further comprising two bit lines, wherein
the latch circuit is coupled to the two bit lines,
one of the two bit lines is selected and the other bit line is non-selected when the latch circuit is in operation, and
one of the two bit lines is coupled to memory cells connected in series in the memory cell array.
22. The semiconductor memory device according to claim 18 , further comprising:
two transistors provided between the latch circuit and the cache circuit.
23. The semiconductor memory device according to claim 18 , further comprising:
a plurality of latch circuits include the latch circuit; and
a plurality of cache circuits include the cache circuit, wherein
the latch circuits and the cache circuits are identical in number.
24. The semiconductor memory device according to claim 18 , farther comprising:
another memory cell array including a plurality of memory cells;
a half of a block is arranged in the memory cell array and another half of the block is arranged in said another memory cell array; and
memory cells in the block are concurrently erasable.
25. The semiconductor memory device according to claim 18 , further comprising:
another memory cell array including a plurality of memory cells, wherein
a block is arranged in the memory cell array or in said another memory cell array, and
memory cells in the block are concurrently erasable.
26. The semiconductor memory device according to claim 18 , further comprising:
another memory cell array including a plurality of memory cells; and
two row decoders provided between the memory cell array and said another memory cell array, wherein
one of the row decoders is coupled to the memory cells, and another row decoder is coupled to said another memory cell array.
27. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells;
a cache circuit configured to hold data input from an I/O pad; and
a latch circuit configured to latch data transferred from the cache circuit and transfer the latched data to at least one of the memory cells, wherein
after the semiconductor memory device receives a first command, a first address, first data, a second command, a third command, a second address, second data, and a fourth command, an operation of inputting the second data to the cache circuit is performed in parallel with and concurrently with an operation of applying a voltage to write the first data to the memory cell in a write operation,
the third command is identical to the first command,
the fourth command is different from the second command, and
the latch circuit ends programming after the semiconductor memory device receives the fourth command.
28. The semiconductor memory device according to claim 27 , wherein the first data and the second data are transferred to an identical block, and
memory cells included in the block are concurrently erasable.
29. The semiconductor memory device according to claim 27 , wherein the latch circuit includes two inverters.
30. The semiconductor memory device according to claim 29 , wherein the cache circuit includes two inverters.
31. The semiconductor memory device according to claim 27 , further comprising a data input/output buffer coupled to the latch circuit via the cache circuit.
32. The semiconductor memory device according to claim 31 , wherein
the data input/output buffer is coupled to the I/O pad.
33. The semiconductor memory device according to claim 31 , wherein
the cache circuit is coupled between a bit line and the data input/output buffer.
34. The semiconductor memory device according to claim 27 , further comprising two bit lines, wherein
the latch circuit is coupled to the two bit lines, and
one of the two bit lines is selected and the other bit line is non-selected when the latch circuit is in operation.