Flash memory device
An integrated circuit product includes a silicon-on-insulator (SOI) substrate and a flash memory device positioned in a first area of the SOI substrate. The SOI substrate includes a semiconductor bulk substrate, a buried insulating layer positioned above the semiconductor bulk substrate, and a semiconductor layer positioned above the buried insulating layer, and the flash memory device includes a flash transistor device and a read transistor device. The flash transistor device includes a floating gate, an insulating layer positioned above the floating gate, and a control gate positioned above the insulating layer, wherein the floating gate includes a portion of the semiconductor layer. The read transistor device includes a gate dielectric layer positioned above the semiconductor bulk substrate and a read gate electrode positioned above the gate dielectric layer.
1. An integrated circuit product, comprising:
a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulating layer positioned above said semiconductor bulk substrate, and a semiconductor layer positioned above said buried insulating layer; and
a flash memory device positioned in a first area of said SOI substrate, said flash memory device comprising:
a flash transistor device comprising a floating gate, an insulating layer positioned above said floating gate, and a control gate positioned above said insulating layer, said floating gate comprising a portion of said semiconductor layer; and
a read transistor device comprising a gate dielectric layer positioned above said semiconductor bulk substrate and a read gate electrode positioned above said gate dielectric layer; and
a fully depleted silicon-on-insulator (FDSOI) transistor device positioned in a second area of said SOI substrate that is electrically isolated from said first area, wherein said FDSOI transistor device comprises a second portion of said semiconductor layer, a high-k gate dielectric layer positioned above said second portion of said semiconductor layer, and a first metal gate layer positioned above said high-k gate dielectric layer.
2. The integrated circuit product of claim 1 , wherein said buried insulating layer is a buried oxide (BOX) layer.
3. The integrated circuit product of claim 1 , wherein said insulating layer is positioned on an upper surface and on sidewall surfaces of said floating gate, and wherein said control gate is positioned on an upper surface and on sidewall surfaces of said insulating layer.
4. The integrated circuit product of claim 1 , wherein said insulating layer is an oxide-nitride-oxide multi-layer.
5. The integrated circuit product of claim 1 , wherein at least one of said flash transistor device and said read transistor device comprises raised source/drain regions.
6. The integrated circuit product of claim 1 , wherein said flash transistor device comprises a first doped well region positioned in said semiconductor bulk substrate below said floating gate and said read transistor device comprises a second doped well region positioned in said semiconductor bulk substrate below said read gate electrode, said first doped well region being doped differently from said second doped well region.
7. An integrated circuit product, comprising:
a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried oxide layer positioned above said semiconductor bulk substrate, and a semiconductor layer positioned above said buried oxide layer;
a flash memory device positioned in a first area of said SOI substrate, said flash memory device comprising:
a flash transistor device comprising a floating gate, an insulating layer positioned on an upper surface of said floating gate, and a control gate positioned on an upper surface of said insulating layer, wherein said floating gate comprises a first portion of said semiconductor layer and said insulating layer comprises an oxide-nitride-oxide multi-layer; and
a read transistor device comprising a gate dielectric layer positioned above said semiconductor bulk substrate and a read gate electrode positioned above said gate dielectric layer; and
a fully depleted silicon-on-insulator (FDSOI) transistor device positioned in a second area of said SOI substrate that is electrically isolated from said first area, wherein said FDSOI transistor device comprises a second portion of said semiconductor layer.
8. The integrated circuit product of claim 7 , wherein said insulating layer is also positioned on sidewall surfaces of said floating gate, and wherein said control gate is also positioned on sidewall surfaces of said insulating layer.
9. The integrated circuit product of claim 7 , wherein at least one of said flash transistor device and said read transistor device comprises raised source/drain regions.
10. The integrated circuit product of claim 7 , wherein said flash transistor device comprises a first doped well region positioned in said semiconductor bulk substrate below said floating gate and said read transistor device comprises a second doped well region positioned in said semiconductor bulk substrate below said read gate electrode, said first doped well region being doped differently from said second doped well region.
11. The integrated circuit product of claim 7 , wherein said FDSOI transistor device further comprises a high-k gate dielectric layer positioned above said second portion of said semiconductor layer, and a first metal gate layer positioned above said high-k gate dielectric layer.
12. The integrated circuit product of claim 11 , wherein at least one of said control gate of said flash transistor device and said read gate electrode of said read transistor device comprises a second metal gate layer.
13. The integrated circuit product of claim 12 , wherein said second metal gate layer is a same material as said first metal gate layer.
14. An integrated circuit product, comprising:
a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulating layer positioned above said semiconductor bulk substrate, and a semiconductor layer positioned above said buried insulating layer; and
a flash memory device positioned in a first area of said SOI substrate, said flash memory device comprising:
a flash transistor device comprising a floating gate, an insulating layer positioned above said floating gate, and a control gate positioned above said insulating layer, said floating gate comprising a portion of said semiconductor layer; and
a read transistor device comprising a gate dielectric layer positioned above said semiconductor bulk substrate and a read gate electrode positioned above said gate dielectric layer, wherein at least one of said control gate of said flash transistor device and said read gate electrode of said read transistor device comprises a first metal gate layer; and
a fully depleted silicon-on-insulator (FDSOI) transistor device positioned in a second area of said SOI substrate that is electrically isolated from said first area, wherein said FDSOI transistor device comprises a second portion of said semiconductor layer, a high-k gate dielectric layer positioned above said second portion of said semiconductor layer, and a second metal gate layer positioned above said high-k gate dielectric layer.
15. The integrated circuit product of claim 14 , wherein said first metal gate layer of said at least one of said control gate and said read gate electrode comprises a same material as said second metal gate layer of said FDSOI transistor device.
16. The integrated circuit product of claim 14 , wherein said buried insulating layer is a buried oxide (BOX) layer.
17. The integrated circuit product of claim 14 , wherein said insulating layer is positioned on an upper surface and on sidewall surfaces of said floating gate, and wherein said control gate is positioned on an upper surface and on sidewall surfaces of said insulating layer.
18. The integrated circuit product of claim 14 , wherein said insulating layer is an oxide-nitride-oxide multi-layer.
19. The integrated circuit product of claim 14 , wherein at least one of said flash transistor device and said read transistor device comprises raised source/drain regions.
20. The integrated circuit product of claim 14 , wherein said flash transistor device comprises a first doped well region positioned in said semiconductor bulk substrate below said floating gate and said read transistor device comprises a second doped well region positioned in said semiconductor bulk substrate below said read gate electrode, said first doped well region being doped differently from said second doped well region.