Method of fabricating DMOS and CMOS transistors
View Patent ↗A method of fabricating a semiconductor device including a diffused metal-oxide-semiconductor (DMOS) transistor, an n-type metal-oxide-semiconductor (NMOS) transistor, and a p-type metal-oxide-semiconductor (PMOS) transistor includes forming separation regions in a semiconductor substrate, forming a gate insulating film, forming a DMOS gate electrode on the gate insulating film, forming a first mask pattern on the semiconductor substrate, performing a first ion implantation process, forming a second mask pattern on the semiconductor substrate, performing a second ion implantation process, forming a third mask pattern on the semiconductor substrate and performing a third ion implantation process into the semiconductor substrate, and forming a fourth mask pattern on the semiconductor substrate and performing a fourth ion implantation process.
1. A semiconductor device, comprising:
a semiconductor substrate;
a gate insulating film formed on the substrate;
a gate electrode formed on the gate insulating film;
a first well region and a second well region formed in the substrate, wherein the first well region and the second well region are in direct contact with each other, and an interface between the first well region and the second well region is disposed below the gate electrode; and
a high concentration drain region formed in the first well region; and
a high concentration source region formed in the second well region,
wherein the first well region is formed to be deeper than the high concentration drain region and is formed to be shallower below the gate electrode than below the high concentration drain region, and
wherein the second well region is formed to be deeper than the high concentration source region and is formed to be shallower below the gate electrode than below the high concentration source region.
2. The semiconductor device of claim 1 , further comprising a field oxide region formed overlapped with the gate electrode and is formed in the first well region.
3. The semiconductor device of claim 1 , wherein the semiconductor device comprises a diffused metal-oxide-semiconductor (DMOS) transistor.
4. The semiconductor device of claim 1 , further comprising:
an buried layer formed in the semiconductor substrate;
a deep trench isolation (DTI) formed deeper than the buried layer; and
a well tab region in the second well region.
5. A semiconductor device, comprising:
a gate insulating film formed in a semiconductor substrate;
a gate electrode formed on the gate insulating film;
a first well region formed overlapping at least in part with a first portion of the gate electrode;
a second well region formed overlapping at least in part with a second portion of the gate electrode; and
an high concentration source region formed in the second well region; and
an high concentration drain region formed in the first well region,
wherein the first well region is formed deeper than the high concentration drain region and is formed shallower below the gate electrode than below the high concentration drain region, and
wherein the second well region is formed deeper than the high concentration source region and is formed shallower below the gate electrode than below the high concentration source region.
6. The semiconductor device of claim 5 , further comprising a field oxide region formed overlapped with the gate electrode and is formed in the first well region.
7. The semiconductor device of claim 5 , wherein the semiconductor device comprises a diffused metal-oxide-semiconductor (DMOS) transistor.
8. The semiconductor device of claim 5 , further comprising:
an buried layer formed in the semiconductor substrate;
a deep trench isolation (DTI) formed deeper than the buried layer; and
a well tab region in the second well region.