Single or multi chip module package and related methods

1. A semiconductor device package having no lead frame consisting of:

at least one die comprising at least one electrical contact;

at least one clip comprising at least one electrical contact mechanically and electrically coupled with the at least one die; and

one of an overmolding or an encapsulating compound enclosed around the at least one die and a majority of the at least one clip.

2. A semiconductor device package comprising:

a plurality of electrical contacts comprised on a first face of a first die;

at least one electrical contact on a first face of a second die;

a first clip mechanically and electrically coupled with an electrical contact on a second face of the second die where the second face of the second die is on an opposing side of the second die from the first face of the second die; and

one of a mold compound or an encapsulating compound enclosed around a second face of the first die opposite the plurality of electrical contacts and enclosed around the second die and a majority of the first clip; and

no lead frame;

wherein the at least one electrical contact on the first face of the second die and the electrical contact of the first clip are not one of overmolded and encapsulated.

3. The semiconductor device package of claim 2 , wherein the portion of the plurality of electrical contacts on the first face of the first die are configured to be positioned to electrically couple with one or more conductive paths comprised in a motherboard, the one or more conductive paths forming a distribution layer.

4. The semiconductor device package of claim 3 , wherein the distribution layer is configured to distribute a majority of electrical signals between the plurality of electrical contacts on the first face of the first die.

5. The semiconductor device package of claim 2 , wherein the first clip is one of bonded or soldered to the second face of the second die.

6. The semiconductor device package of claim 2 , wherein the distribution layer is configured to distribute all electrical communication among and between each die and each clip of the semiconductor device package.

7. The semiconductor device package of claim 2 , further comprising:

at least one electrical contact on a first face of a third die;

a second clip mechanically and electrically coupled with an electrical contact on a second face of the third die, the second face of the third die on an opposing side of the third die from the first face of the third die;

wherein the third die and a majority of the second clip are one of overmolded or encapsulated; and

wherein the at least one electrical contact on the first face of the third die and the electrical contact of the second clip are not one of overmolded or encapsulated.

8. The semiconductor device package of claim 7 , wherein the distribution layer is configured to distribute all electrical communication between the first die, the second die and the third die.

9. The semiconductor device package of claim 7 , wherein the second clip is positioned to electrically couple the second die with the third die.

10. The semiconductor device package of claim 7 , wherein the electrical contact of the second clip is positioned to electrically couple with the one or more conductive paths comprised in a motherboard.

11. The semiconductor device package of claim 2 , wherein the semiconductor device package comprises no wire bonds.

12. A semiconductor device package comprising:

a plurality of electrical contacts on a first face of a first die;

a passive component;

at least one clip electrically and mechanically coupled with at least one electrical contact on a second face of the first die;

one of a mold compound or an encapsulating compound enclosed around a second face of the first die, the passive component opposite the plurality of electrical contacts, and a majority of the at least one clip; and

no lead frame.

13. The semiconductor device package of claim 12 , further comprising no wire bonds.

14. The semiconductor device package of claim 12 , wherein the plurality of electrical contacts on the first face of the first die comprise one of pads or bumps.

15. The semiconductor device package of claim 12 , wherein the portion of the plurality of electrical contacts on the first face of the first die are configured to be positioned to electrically couple with one or more conductive paths comprised in a motherboard, the one or more conductive paths forming a distribution layer.

16. The semiconductor device package of claim 15 , further comprising at least one electrical contact on a first face of a second die; and

a first clip mechanically and electrically coupled with an electrical contact on a second face of the second die where the second face of the second die is on an opposing side of the second die from the first face of the second die;

wherein one of a mold compound or an encapsulating compound enclose the second die and a majority of the first clip; and

wherein the at least one electrical contact on the first face of the second die and the electrical contact of the first clip are not one of overmolded or encapsulated.

17. The semiconductor device package of claim 16 , wherein the distribution layer is configured to distribute all electrical communication among and between the first die and the second die and the first clip of the semiconductor device package.

18. The semiconductor device package of claim 12 , wherein the at least one clip is mechanically coupled with the at least one electrical contact through one of bonding or soldering on the second face of the first die.