IP Library Granted Patent US 10,217,813
Granted Patent B2
US 10,217,813 · App. 15/836,348 · Granted Feb 26, 2019

Method for manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device

Inventor: Toru Hiyoshi (Osaka, JP)
Assignee: Sumitomo Electric Industries, Ltd.
H01L29/0634H01L21/0262H01L21/02378H01L21/02447H01L21/02494H01L21/02529H01L21/02576H01L21/02579H01L21/02658H01L21/0455H01L21/0475H01L29/1095H01L29/1608H01L29/66068H01L29/7395H01L29/7802H01L29/861H01L29/6606H01L29/872
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Quick Facts
Patent No.
US 10,217,813
App. No.
15/836,348
Granted
Feb 26, 2019
Kind
B2
Abstract

A method for manufacturing a silicon carbide semiconductor device includes the steps of preparing a silicon carbide substrate having a first main surface and a second main surface located on a side opposite to the first main surface, forming an epitaxial layer on the first main surface, the epitaxial layer having a first conductivity type and having a third main surface located on a side opposite to a side on which the silicon carbide substrate is located, forming a trench, which includes side walls intersecting with the third main surface and a bottom portion connected to the side walls, in the epitaxial layer, widening an opening of the trench, and forming an embedded region, which has a second conductivity type different from the first conductivity type, in the trench. The epitaxial layer adjacent to the embedded region and the embedded region constitute a superjunction structure.

Claims (18)

1. A silicon carbide semiconductor device comprising:

a silicon carbide substrate having a first main surface and a second main surface located on a side opposite to said first main surface;

an epitaxial layer formed on said first main surface, said epitaxial layer having a first conductivity type and having a third main surface located on a side opposite to a side on which said silicon carbide substrate is located;

a trench which is formed in said epitaxial layer and includes side walls intersecting with said third main surface and a bottom portion connected to said side walls; and

an embedded region, which is formed in said trench and has a second conductivity type different from said first conductivity type, said trench being filled with said embedded region;

an opening of said trench being wider than said bottom portion, and said epitaxial layer adjacent to said embedded region and said embedded region constituting a superjunction structure, said silicon carbide semiconductor device further comprising:

an impurity region formed on said embedded region and having said second conductivity type;

a first electrode provided on said impurity region; and

a second electrode in contact with said second main surface.

2. The silicon carbide semiconductor device according to claim 1 , wherein said side walls are inclined by greater than or equal to 45° and less than or equal to 80° with respect to said third main surface.

3. The silicon carbide semiconductor device according to claim 1 , wherein

in said embedded region, a concentration of an impurity having said second conductivity type is reduced from said bottom portion toward said opening, and

in said epitaxial layer, a concentration of an impurity having said first conductivity type increases from said first main surface toward said third main surface.

4. The silicon carbide semiconductor device according to claim 1 , wherein said embedded region is in contact with said impurity region.

5. The silicon carbide semiconductor device according to claim 1 , wherein said bottom portion is in contact with said first main surface.

6. The silicon carbide semiconductor device according to claim 1 , wherein said trench extends along a <11-20>direction when viewed in a plan view.

7. The silicon carbide semiconductor device according to claim 6 , wherein a plurality of trenches and embedded regions are provided, and

the plurality of said trenches and said embedded regions are in stripe.

Assignments (2)
NUNC PRO TUNC ASSIGNMENT Recorded Jul 1, 2026
From: SUMITOMO ELECTRIC INDUSTRIES, LTD.
To: MITSUMI ELECTRIC CO., LTD.
Reel/Frame 075871/0320 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2017
From: HIYOSHI, TORU
To: SUMITOMO ELECTRIC INDUSTRIES, LTD.
Reel/Frame 044342/0250 →
Priority Claims (1)
JP 2014-193764 · Sep 24, 2014 · national
Continuity (2)
Division 14831580 · Aug 20, 2015
Related Publication 20180108730A1 · Apr 19, 2018
Cited By (1)
US 12,336,234