Methods of simultaneously forming bottom and top spacers on a vertical transistor device
A vertical transistor device includes a vertically oriented channel semiconductor structure, a bottom source/drain (S/D) region, a top source/drain (S/D) region, and a gate structure positioned around the vertically oriented channel semiconductor structure, above the bottom source/drain (S/D) region, and below the top source/drain (S/D) region. The gate structure includes a gate electrode and a gate insulation layer positioned between the gate electrode and at least a portion of the vertically oriented channel semiconductor structure. A top spacer is positioned between the gate electrode and at least a portion of the top source/drain (S/D) region, a bottom spacer is positioned between the gate electrode and at least a portion of the bottom source/drain (S/D) region, and a gate cap is positioned around an outer perimeter surface of the gate structure, wherein the top spacer, the bottom spacer, and the gate cap all include a same insulating material.
1. A vertical transistor device, comprising:
a vertically oriented channel semiconductor structure;
a bottom source/drain (S/D) region;
a top source/drain (S/D) region;
a gate structure positioned around said vertically oriented channel semiconductor structure, above said bottom source/drain (S/D) region, and below said top source/drain (S/D) region, said gate structure comprising a gate electrode and a gate insulation layer that is positioned between said gate electrode and at least a portion of said vertically oriented channel semiconductor structure;
a top spacer positioned between said gate electrode and at least a portion of said top source/drain (S/D) region;
a bottom spacer positioned between said gate electrode and at least a portion of said bottom source/drain (S/D) region; and
a gate cap positioned around an outer perimeter surface of said gate structure, wherein said top spacer, said bottom spacer, and said gate cap all comprise a same insulating material, and said top spacer, said bottom spacer, and said gate cap comprise a unitary and contiguous structure.
2. The vertical transistor device of claim 1 , wherein said gate insulation layer comprises a high-k material having a dielectric constant of approximately 10 or greater.
3. The vertical transistor device of claim 1 , wherein said same insulating material comprising said top spacer, said bottom spacer, and said gate cap structure is a low-k material having a dielectric constant of approximately 7 or less.
4. The vertical transistor device of claim 1 , wherein said gate cap extends from said top spacer to said bottom spacer.
5. The vertical transistor device of claim 1 , wherein said top spacer, said bottom spacer and said gate cap comprise a unitary and contiguous structure.
6. The vertical transistor device of claim 1 , wherein said top spacer is formed on and in contact with said gate electrode and on and in contact with said upper source/drain (S/D) region.
7. The vertical transistor device of claim 1 , wherein said bottom spacer is formed on and in contact with said gate electrode and on and in contact with said bottom source/drain (S/D) region.
8. The vertical transistor device of claim 1 , wherein said gate electrode comprises at least one material layer comprising a metal.
9. A vertical transistor device, comprising:
a vertically oriented channel semiconductor structure;
a bottom source/drain (S/D) region positioned on and in contact with a lower end portion of said vertically oriented channel semiconductor structure;
a top source/drain (S/D) region positioned on and in contact with an upper end portion of said vertically oriented channel semiconductor structure;
a gate structure positioned above said bottom source/drain (S/D) region, below said top source/drain (S/D) region, and surrounding a center portion of said vertically oriented channel semiconductor structure; and
a unitary and contiguous insulating structure surrounding at least said gate structure and said vertically oriented channel semiconductor structure, said insulating structure comprising:
a top spacer portion positioned between said gate structure and at least a portion of said top source/drain (S/D) region; and
a bottom spacer portion positioned between said gate structure and at least a portion of said bottom source/drain (S/D) region.
10. The vertical transistor device of claim 9 , wherein said insulating structure further comprises a gate cap portion that is positioned around an outer perimeter surface of said gate structure and extends from said top spacer portion to said bottom spacer portion.
11. The vertical transistor device of claim 10 , wherein all portions of said insulating structure comprise a same insulating material.
12. The vertical transistor device of claim 11 , wherein said same insulating material comprising said all of said portions of said insulating structure is a low-k material having a dielectric constant of approximately 7 or less.
13. The vertical transistor device of claim 9 , wherein said gate structure comprises a gate electrode and a gate insulation layer that is positioned between said gate electrode and said center portion of said vertically oriented channel semiconductor structure.
14. The vertical transistor device of claim 13 , wherein said gate insulation layer comprises a high-k material having a dielectric constant of approximately 10 or greater.
15. The vertical transistor device of claim 13 , wherein said gate electrode comprises at least one material layer comprising a metal.
16. A vertical transistor device, comprising:
a vertically oriented channel semiconductor structure;
a bottom source/drain (S/D) region positioned on and in contact with a lower end portion of said vertically oriented channel semiconductor structure;
a top source/drain (S/D) region positioned on and in contact with an upper end portion of said vertically oriented channel semiconductor structure;
a gate structure positioned above said bottom source/drain (S/D) region, below said top source/drain (S/D) region, and surrounding a center portion of said vertically oriented channel semiconductor structure that is positioned between said upper and lower end portions of said vertically oriented channel semiconductor structure, said gate structure comprising a gate electrode and a gate insulation layer that is positioned between said gate electrode and said center portion of said vertically oriented channel semiconductor structure; and
a unitary and contiguous insulating structure, said insulating structure comprising:
a top spacer portion positioned between said gate structure and at least a portion of said top source/drain (S/D) region;
a bottom spacer portion positioned between said gate structure and at least a portion of said bottom source/drain (S/D) region; and
a gate cap portion positioned around an outer perimeter surface of said gate structure and extending from said top spacer portion to said bottom spacer portion, wherein each of said top spacer portion, said bottom spacer portion, and said gate cap portion of said insulating structure comprise a same insulating material.
17. The vertical transistor device of claim 16 , wherein said same insulating material comprising each of said top spacer portion, said bottom spacer portion, and said gate cap portion of said insulating structure is a low-k material having a dielectric constant of approximately 7 or less.
18. The vertical transistor device of claim 16 , wherein said gate insulation layer comprises a high-k material having a dielectric constant of approximately 10 or greater.
19. The vertical transistor device of claim 18 , wherein said gate electrode comprises at least one material layer comprising a metal.