Method and apparatus for dynamic calibration of on-die-precision-resistors

1. An apparatus, comprising:

a semiconductor chip;

a precision resistor array on the semiconductor chip;

a replica precision resistor array on the semiconductor chip, the replica precision resistor array being configured to mimic the resistance behavior of the precision resistor array and having a characteristic resistance that is a function of temperature; and

wherein the semiconductor chip being configured to calibrate the precision resistor array using the characterized resistance as a function of temperature, a resistance offset of the precision resistor array relative to the characterized resistance as a function of temperature, and a temperature of the precision resistor array.

2. The apparatus of claim 1 , comprising an I/O logic block operable to drive signals to an I/O.

3. The apparatus of claim 2 , wherein the I/O logic block comprises an impedance compensation circuit operable to maintain the driven signals at a target impedance using a resistance of the precision resistor array.

4. The apparatus of claim 1 , comprising a temperature sensor proximate the precision resistor array to sense the temperature of the precision resistor array.

5. The apparatus of claim 1 , comprising a storage device to store the characterized resistance as a function of temperature of the replica precision resistor array and the resistance offset of the precision resistor array relative to the characterized resistance as a function of temperature.

6. The apparatus of claim 1 , comprising plural replica precision resistor arrays positioned at different positions on the semiconductor chip.

7. A method of manufacturing, comprising:

fabricating a precision resistor array on a semiconductor chip;

a replica precision resistor array on the semiconductor chip, the replica precision resistor array being configured to mimic the resistance behavior of the precision resistor array and having a characteristic resistance that is a function of temperature; and

fabricating logic on the semiconductor chip configured to calibrate the precision resistor array using the characterized resistance as a function of temperature, a resistance offset of the precision resistor array relative to the characterized resistance as a function of temperature, and a temperature of the precision resistor array.

8. The method of claim 7 , comprising fabricating an I/O logic block and an I/O on the semiconductor chip, the I/O logic block being operable to drive signals to the I/O.

9. The method of claim 8 , wherein the I/O logic block comprises an impedance compensation circuit operable to maintain the driven signals at a target impedance using a resistance of the precision resistor array.

10. The method of claim 7 , comprising fabricating a temperature sensor proximate the precision resistor array to sense the temperature of the precision resistor array.

11. The method of claim 7 , fabricating a storage device on the semiconductor chip to store the characterized resistance as a function of temperature of the replica precision resistor array and the resistance offset of the precision resistor array relative to the characterized resistance as a function of temperature.

12. The method of claim 7 , comprising fabricating plural replica precision resistor arrays positioned at different positions on the semiconductor chip.

13. A method of operating a semiconductor chip having a precision resistor array and a replica precision resistor array being configured to mimic the resistance behavior of the precision resistor array, comprising:

characterizing the resistance of the replica precision resistor array as a function of temperature;

determining a resistance offset of the precision resistor array relative to the characterized resistance as a function of temperature; and

calibrating the precision resistor array using the characterized resistance as a function of temperature, the resistance offset of the precision resistor array relative to the characterized resistance as a function of temperature, and a temperature of the precision resistor array.

14. The method of claim 13 , comprising performing the calibration of the precision resistor array when a condition triggering a requirement for new calibration is presented.

15. The method of claim 14 , when the condition comprises a temperature change of the precision resistor array above a preselected threshold, a change in peripheral connected to the semiconductor chip or an age of the semiconductor chip.

16. The method of claim 13 , wherein the semiconductor chip comprises an I/O logic block and an I/O, the method comprising using the I/O logic block to drive signals to the I/O.

17. The method of claim 16 , wherein the I/O logic block comprises an impedance compensation circuit operable to maintain the driven signals at a target impedance using a resistance of the precision resistor array.

18. The method of claim 13 , comprising using a temperature sensor proximate the precision resistor array to sense the temperature of the precision resistor array.

19. The method of claim 13 , wherein the semiconductor chip comprises a storage device, the method comprising storing in the storage device the characterized resistance as a function of temperature of the replica precision resistor array and the resistance offset of the precision resistor array relative to the characterized resistance as a function of temperature.

20. The method of claim 13 , wherein the semiconductor chip comprises plural replica precision resistor arrays positioned at different positions on the semiconductor chip.