Forming silicon oxide layers by radical oxidation and semiconductor device with silicon oxide layer
A body structure and a drift zone are formed in a semiconductor layer, wherein the body structure and the drift zone form a first pn junction. A silicon nitride layer is formed on the semiconductor layer. A silicon oxide layer is formed from at least a vertical section of the silicon nitride layer by oxygen radical oxidation.
1. A method of manufacturing a semiconductor device, the method comprising:
forming a body structure and a drift zone in a semiconductor layer, wherein the body structure and the drift zone form a first pn junction;
forming, during a first iteration, a first silicon nitride layer on the semiconductor layer;
forming, during the first iteration, a first silicon oxide layer from at least a vertical section of the first silicon nitride layer by oxygen radical oxidation; and
performing a second iteration including (i) forming a second silicon nitride layer on a portion of the first silicon oxide layer formed in the first iteration and (ii) transforming the second silicon nitride layer into a second silicon oxide layer by oxygen radical oxidation.
2. The method of claim 1 , wherein the silicon oxide layer has a thickness of at least 15 nm.
3. The method of claim 1 , wherein the first silicon nitride layer is formed directly on the semiconductor layer.
4. The method of claim 1 , further comprising:
forming, before forming the first silicon nitride layer, a dielectric intermediate layer directly on the semiconductor layer, wherein the first silicon nitride layer is formed directly on the dielectric intermediate layer.
5. The method of claim 4 , wherein the dielectric intermediate layer is from silicon oxide.
6. The method of claim 4 , wherein the dielectric intermediate layer has a thickness of at least 3 nm.
7. The method of claim 1 , wherein the semiconductor layer is based on silicon carbide.
8. The method of claim 1 , wherein forming the first silicon oxide layer comprises a co-injection of molecular oxygen O 2 and molecular hydrogen H 2 into a process chamber at conditions inhibiting a reaction of molecular oxygen O 2 and molecular hydrogen H 2 in a gas phase.
9. The method of claim 8 , wherein the first silicon oxide layer is formed at a temperature below 300° C.
10. The method of claim 1 , wherein forming the first silicon oxide layer comprises an injection of molecular oxygen O 2 or a mixture of molecular oxygen O 2 and molecular hydrogen H 2 into a process chamber at conditions inhibiting a reaction of molecular oxygen O 2 and molecular hydrogen H 2 in a gas phase and forming a microwave plasma along a front side of the semiconductor layer.
11. The method of claim 1 , wherein the oxygen radical oxidation is terminated before the oxygen radical oxidation completely consumes the first silicon nitride layer.
12. The method of claim 1 , wherein the oxygen radical oxidation is terminated with the first silicon nitride layer completely consumed by the oxygen radical oxidation.
13. The method of claim 1 , wherein the oxygen radical oxidation is terminated after the oxygen radical oxidation has consumed a portion of the semiconductor layer.
14. The method of claim 1 , wherein the first silicon nitride layer is formed by low-pressure chemical vapor deposition.
15. The method of claim 1 , further comprising:
forming a dielectric supplementary layer directly on the second silicon oxide layer.
16. The method of claim 1 , further comprising:
forming gate trenches extending from a front surface at a front side into the body structure, wherein the first silicon oxide layer is formed parallel to sidewalls of the gate trenches.
17. The method of claim 1 , further comprising:
forming a gate electrode on the second silicon oxide layer.
18. The method of claim 17 , further comprising:
forming a plurality of electrically connected source zones forming second pn junctions with the body structure.
19. The method of claim 1 , further comprising:
forming a plurality of interconnected gate electrodes of transistor cells electrically connected in parallel to each other.
20. The method of claim 1 , wherein the second silicon oxide layer forms a further portion of the first silicon oxide layer.
21. The method of claim 1 , further comprising:
performing a third iteration including (i) forming a third silicon nitride layer on a portion of the second silicon oxide layer formed in the second iteration and (ii) transforming the third silicon nitride layer into a third silicon oxide layer by oxygen radical oxidation.
22. The method of claim 21 , wherein the third silicon oxide layer forms a further portion of the second silicon oxide layer.
23. The method of claim 21 , wherein the third silicon oxide layer forms a further portion of the first silicon oxide layer and the second silicon oxide layer.
24. The method of claim 21 , further comprising:
forming a dielectric supplementary layer directly on the third silicon oxide layer.
25. The method of claim 21 , further comprising:
forming a gate electrode on the third silicon oxide layer.
26. The method of claim 21 , further comprising:
performing a further iteration including (i) forming a further silicon nitride layer on a portion of the third silicon oxide layer formed in the third iteration and (ii) transforming the further silicon nitride layer into a further silicon oxide layer by oxygen radical oxidation.
27. The method of claim 1 , further comprising:
performing a plurality of further iterations on the second silicon oxide layer, the plurality of further iterations comprising (i) forming a further silicon nitride layer and (ii) transforming the further silicon nitride layer into a further silicon oxide layer by oxygen radical oxidation, wherein the further silicon nitride layer of iteration (m) is formed on a portion of the further silicon oxide layer formed in iteration (m−1), wherein the iteration (m) and the iteration (m−1) are adjacent iterations and the iteration (m) is performed subsequent to the iteration (m−1), where m is an integer.