Method for integrating a light emitting device
Light emitting devices and methods of integrating micro LED devices into light emitting device are described. In an embodiment a light emitting device includes a reflective bank structure within a bank layer, and a conductive line atop the bank layer and elevated above the reflective bank structure. A micro LED device is within the reflective bank structure and a passivation layer is over the bank layer and laterally around the micro LED device within the reflective bank structure. A portion of the micro LED device and a conductive line atop the bank layer protrude above a top surface of the passivation layer.
1. A display panel comprising:
a substrate;
a plurality of light emitting diode (LEDs) on the substrate and within a pixel area of the display panel;
a plurality of Vss tie lines in the substrate and extending across the pixel area of the display panel;
wherein the substrate further comprises a planarization layer over the plurality of Vss tie lines, and the LEDs are over the planarization layer;
a patterned dam layer over the planarization layer;
a metal layer on top of the patterned dam layer, wherein the metal layer is in electrical contact with the plurality of Vss tie lines; and
one or more top conductive electrode layers that electrically connect the plurality of LEDs with the plurality of Vss tie lines.
2. The display panel of claim 1 , wherein the plurality of Vss tie lines run in a row-wise direction across the pixel area.
3. The display panel of claim 1 , wherein the plurality of Vss tie lines run in a column-wise direction across the pixel area.
4. The display panel of claim 1 , wherein the plurality of Vss tie lines run in both a row-wise direction and column-wise direction across the pixel area.
5. The display panel of claim 1 , wherein the plurality of Vss tie lines are coupled to a flexible circuit board (FCB).
6. The display panel of claim 1 , further comprising a passivation layer over the substrate and laterally around the plurality of LEDs.
7. The display panel of claim 6 , wherein the one or more top conductive electrode layers are over the passivation layer.
8. The display panel of claim 7 , wherein the plurality of Vss tie lines run in a row-wise direction across the pixel area.
9. The display panel of claim 7 , wherein the plurality of Vss tie lines run in a column-wise direction across the pixel area.
10. The display panel of claim 7 , wherein the plurality of Vss tie lines run in both a row-wise direction and column-wise direction across the pixel area.
11. The display panel of claim 1 , wherein the one or more top conductive electrodes are in direct contact with the metal layer on top of the patterned dam layer.
12. The display panel of claim 1 , the metal layer comprises a plurality of via contacts electrically connected to the plurality of Vss tie lines.
13. The display panel of claim 1 , further comprising:
a passivation layer over the substrate and laterally around the plurality of LEDs, wherein the one or more top conductive electrode layers are over the passivation layer; and
a plurality of recesses in a top surface of the passivation layer to expose the plurality of LEDs, wherein the one or more top conductive electrodes contact the plurality of LEDs in the plurality of recesses.
14. The display panel of claim 13 , wherein the passivation layer comprises a thermoset material.
15. The display panel of claim 14 , wherein the thermoset material is an acrylic.
16. The display panel of claim 13 , wherein each LED comprises a vertical p-n diode between a bottom contact and a top contact.