Reduced resistance source and drain extensions in vertical field effect transistors
View Patent ↗Semiconductor devices and methods of forming the same include forming a bottom source/drain region in a semiconductor substrate under a semiconductor fin. First charged spacers are formed on sidewalls of the semiconductor fin. A gate stack is formed on the fin, over the first charged spacers. Second charged spacers are formed on sidewalls of the fin above the gate stack. The fin is recessed to a height below a top level of the second charged spacers. A top source/drain region is grown from the recessed fin.
1. A method for forming a semiconductor device, comprising:
forming a bottom source/drain region in a semiconductor substrate under a semiconductor fin;
forming first charged spacers on sidewalls of the semiconductor fin;
forming a gate stack on the fin, over the first charged spacers;
forming second charged spacers on sidewalls of the fin above the gate stack;
recessing the fin to a height below a top level of the second charged spacers; and
growing a top source/drain region from the recessed fin.
2. The method of claim 1 , further comprising forming a bottom spacer on the bottom source/drain region after forming the first charged spacers.
3. The method of claim 2 , further comprising etching away material from the first charged spacers that is above a top level of the bottom spacer.
4. The method of claim 1 , further comprising forming an upper spacer on the gate stack after forming the second charged spacers.
5. The method of claim 4 , further comprising etching away material from the second charged spacers that is above a top level of the upper spacer.
6. The method of claim 1 , wherein forming the bottom source/drain region comprises implanting dopants in the semiconductor substrate and annealing the substrate such that dopants diffuse into a lower portion of the fin.
7. The method of claim 1 , wherein recessing the fin comprises recessing the fin to a level above a top surface of the gate stack.
8. The method of claim 1 , wherein the first and second charged layers comprise a material selected from the group consisting of charged silicon nitride and charged aluminum oxide.
9. A semiconductor device, comprising:
one or more semiconductor fins formed on a semiconductor substrate;
a bottom source/drain region formed in the semiconductor substrate;
a lower spacer formed above the bottom source/drain region;
first charged spacers formed on sidewalls of the semiconductor fins;
a gate stack formed above the first charged spacers and the lower spacer;
second charged spacers formed on sidewalls of the semiconductor fins above the gate stack; and
a top source/drain region formed above the gate stack.
10. The semiconductor device of claim 9 , further comprising a lower spacer formed between the bottom source/drain region and the gate stack.
11. The semiconductor device of claim 10 , wherein the first charged spacers have a height that is the same as a height of the lower spacer.
12. The semiconductor device of claim 9 , further comprising an upper spacer formed between the gate stack and the top source/drain region.
13. The semiconductor device of claim 12 , wherein the second charged spacers have a height that is the same as a height of the upper spacer.
14. The semiconductor device of claim 9 , wherein the top source/drain region contacts the semiconductor fins at a height above the gate stack.
15. The semiconductor device of claim 9 , wherein the first and second charged layers comprise a material selected from the group consisting of charged silicon nitride and charged aluminum oxide.
16. A method for forming a semiconductor device, comprising:
forming a bottom source/drain region in a semiconductor substrate under a semiconductor fin;
forming first charged spacers on sidewalls of the semiconductor fin;
forming a bottom spacer on the bottom source/drain region after forming the first charged spacers;
forming a gate stack on the fin, over the first charged spacers;
forming second charged spacers on sidewalls of the fin above the gate stack;
recessing the fin to a height below a top level of the second charged spacers; and
growing a top source/drain region from the recessed fin.
17. The method of claim 16 , further comprising forming an upper spacer on the gate stack after forming the second charged spacers.
18. The method of claim 17 , further comprising etching away material from the second charged spacers that is above a top level of the upper spacer.
19. The method of claim 16 , wherein recessing the fin comprises recessing the fin to a level above a top surface of the gate stack.
20. The method of claim 16 , wherein the first and second charged layers comprise a material selected from the group consisting of charged silicon nitride and charged aluminum oxide.