Semiconductor device package and method of forming semiconductor device package
A semiconductor device package includes a redistribution structure, a first semiconductor device, a plurality of second semiconductor devices, at least one warpage adjusting component, and an encapsulating material. The first semiconductor device is disposed on the redistribution structure. The second semiconductor devices are disposed on the redistribution structure and surround the first semiconductor device. The at least one warpage adjusting component is disposed on at least one of the second semiconductor devices. The encapsulating material encapsulates the first semiconductor device, the second semiconductor devices and the warpage adjusting component, wherein a Young's modulus of the warpage adjusting component is greater than or equal to a Young's modulus of the encapsulating material, and a coefficient of thermal expansion (CTE) of the warpage adjusting component is smaller than a CTE of the encapsulating material.
1. A semiconductor device package comprising:
a redistribution structure;
a first semiconductor device disposed on the redistribution structure;
a plurality of second semiconductor devices disposed on the redistribution structure;
at least one warpage adjusting component disposed on at least one of the second semiconductor devices; and
an encapsulating material encapsulating the first semiconductor device, the second semiconductor devices and the warpage adjusting component, wherein a Young's modulus of the warpage adjusting component is greater than or equal to a Young's modulus of the encapsulating material.
2. The semiconductor device package as claimed in claim 1 , wherein the redistribution structure is a fan-out redistribution structure comprising a plurality of redistribution lines (RDLs) and a plurality of dielectric layers stacked alternately on top of one another, and the encapsulating material is extended over the redistribution structure.
3. The semiconductor device package as claimed in claim 1 , wherein a coefficient of thermal expansion (CTE) of the warpage adjusting component is smaller than a CTE of the encapsulating material.
4. The semiconductor device package as claimed in claim 1 , wherein the first semiconductor device is a system on chip (SOC), and each of the second semiconductor devices is a dynamic random access memory (DRAM) chip-scale package (CSP).
5. The semiconductor device package as claimed in claim 1 , wherein the at least one warpage adjusting component is attached to a back surface of the at least one of the second semiconductor devices via a die attach film, and the back surface faces away from the redistribution structure.
6. The semiconductor device package as claimed in claim 1 , wherein the number of the at least one warpage adjusting component is plural, and the warpage adjusting components are disposed on at least a set of the second semiconductor devices respectively.
7. The semiconductor device package as claimed in claim 6 , wherein sizes of the warpage adjusting components are substantially the same.
8. The semiconductor device package as claimed in claim 6 , wherein a size of one of the warpage adjusting components is different from a size of another one of the warpage adjusting components.
9. The semiconductor device package as claimed in claim 1 , wherein a thickness of the first semiconductor device is greater than a thickness of each of the second semiconductor devices, and the encapsulating material reveals a back surface of the first semiconductor device.
10. A semiconductor device package comprising:
a redistribution structure;
a first semiconductor device disposed on the redistribution structure;
a plurality of second semiconductor devices disposed on the redistribution structure;
an encapsulating material encapsulating the first semiconductor device and the second semiconductor devices; and
a warpage adjusting frame disposed on the encapsulating material and superimposed with the second semiconductor devices.
11. The semiconductor device package as claimed in claim 10 , wherein the material of the warpage adjusting frame comprises stainless steel, copper, aluminum or wolfram.
12. The semiconductor device package as claimed in claim 10 , wherein encapsulating material reveals a back surface of the first semiconductor device and back surfaces of the second semiconductor devices, and a top surface of the encapsulating material is coplanar with the back surface of the first semiconductor device and the back surfaces of the second semiconductor devices.
13. The semiconductor device package as claimed in claim 12 , wherein and the warpage adjusting frame is in a ring form, which is in contact with the encapsulating material and the back surfaces of the second semiconductor devices and reveals the back surface of the first semiconductor device.
14. The semiconductor device package as claimed in claim 10 , wherein the warpage adjusting frame is in a lid form, which is in contact with the encapsulating material, the back surface of the first semiconductor device and the back surfaces of the second semiconductor devices.