Methods of manufacturing a semiconductor device with a buried doped region and a contact structure
A method of manufacturing a semiconductor device includes: forming a doped region in a semiconductor substrate at a first distance to a main surface plane of the semiconductor substrate, wherein the doped region is a first section of a semiconductor column extending from the main surface plane into the semiconductor substrate; forming an insulator structure surrounding at least a second section of the semiconductor column between the main surface plane and the first section in planes parallel to the main surface plane; removing the second section of the semiconductor column; and forming a contact structure extending from the main surface plane to the doped region, wherein the contact structure includes a fill structure and a contact layer, the contact layer formed from a metal semiconductor alloy and directly adjoining the doped region and the fill structure formed from a metal and/or a conductive metal compound.
1. A method of manufacturing a semiconductor device, the method comprising:
forming a doped region in a semiconductor substrate at a first distance to a main surface plane of the semiconductor substrate, wherein the doped region is a first section of a semiconductor column extending from the main surface plane into the semiconductor substrate;
forming an insulator structure surrounding at least a second section of the semiconductor column between the main surface plane and the first section in planes parallel to the main surface plane;
after forming the insulator structure, removing the second section of the semiconductor column; and
forming a contact structure extending from the main surface plane to the doped region, wherein the contact structure comprises a fill structure and a contact layer, the contact layer formed from a metal semiconductor alloy and directly adjoining the doped region and the fill structure formed from a metal and/or a conductive metal compound.
2. The method of claim 1 , wherein the doped region is formed in the first section of the semiconductor column after removing the second section of the semiconductor column.
3. The method of claim 1 , further comprising:
etching first trench sections into the semiconductor substrate from the main surface plane to a base plane, wherein a portion of the semiconductor substrate between the first trench sections forms a portion of the semiconductor column; and
etching, starting from the base plane, second trench sections into the semiconductor substrate, wherein a portion of the semiconductor substrate between the second trench sections forms a semiconductor fin.
4. The method of claim 1 , wherein the insulator structure is formed at least in portions of the first trench sections and the doped region is formed in the semiconductor column.
5. The method of claim 1 , wherein the insulator structure vertically extends deeper into the semiconductor substrate than the contact structure, the depth of the insulator structure and the contact structure being measured from the main surface plane of the semiconductor substrate.
6. A method of manufacturing a semiconductor device, the method comprising:
forming a buried doped region at a first distance from a main surface plane in a semiconductor body;
forming a contact structure extending from the main surface plane to the doped region, wherein the contact structure comprises a contact layer directly adjoining the doped region and a fill structure, wherein the contact layer is formed from a metal semiconductor alloy and the fill structure comprises a metal or a conductive metal compound; and
forming an insulator structure surrounding the contact structure in planes parallel to the main surface plane, wherein the insulator structure laterally directly adjoins the contact structure, wherein the insulator structure vertically extends deeper into the semiconductor body than the contact structure, the depth of the insulator structure and the contact structure being measured from the main surface.
7. The method of claim 6 , wherein forming the buried doped region comprises:
forming a buried connection layer connecting source or drain regions of a plurality of transistor cells formed in the semiconductor body.
8. The method of claim 6 , further comprising:
forming a semiconductor fin in the semiconductor body in a second distance to the main surface plane, the semiconductor fin comprising a channel region; and
forming a first semiconductor column spaced from the main surface plane and directly adjoining the semiconductor fin, wherein the first semiconductor column comprises the doped region, wherein the doped region forms a first homojunction with the channel region.
9. The method of claim 8 , further comprising:
forming a second semiconductor column directly adjoining the semiconductor fin at a side opposite to the first semiconductor column, the second semiconductor column comprising a drain region forming a second homojunction with the channel region.
10. The method of claim 9 , wherein the drain region extends from the main surface plane to the semiconductor fin and includes a drift zone forming the second homojunction and a drain contact zone, and wherein a maximum net dopant concentration in the drain contact zone exceeds at least ten times a mean net dopant concentration in the drift zone.
11. The method of claim 9 , further comprising:
connecting the semiconductor fin to the first semiconductor column and to the second semiconductor column.
12. The method of claim 9 , further comprising:
connecting the first and the second semiconductor columns via at least two semiconductor fins.
13. The method of claim 8 , wherein the first homojunction is a pn junction.
14. The method of claim 8 , further comprising:
forming a gate electrode structure directly adjoining the semiconductor fin on opposite sides, the gate electrode structure comprising a gate electrode and a gate dielectric separating the gate electrode from the semiconductor body.
15. The method of claim 6 , wherein the metal semiconductor alloy is a titanium silicide.
16. The method of claim 6 , wherein a width of the contact structure in a direction parallel to the main surface plane is at most 75 nm.
17. The method of claim 16 , wherein a ratio between the first distance and the width of the contact structure is at least 10:1.
18. A method of manufacturing a semiconductor device, the method comprising:
forming a semiconductor fin in a semiconductor body at a distance to a main surface plane of the semiconductor body, the semiconductor fin comprising a channel region;
forming a first semiconductor column spaced from the main surface plane and directly adjoining the semiconductor fin, the first semiconductor column comprising a source region that forms a first homojunction with the channel region;
forming a contact structure extending from the main surface plane to the first semiconductor column, wherein the contact structure comprises a contact layer formed from a metal semiconductor alloy directly adjoining the first semiconductor column and a fill structure comprising a metal or a conductive metal compound; and
forming an insulator structure laterally directly adjoining the contact structure.
19. The method of claim 18 , further comprising:
forming a second semiconductor column directly adjoining the semiconductor fin at a side opposite to the first semiconductor column, the second semiconductor column comprising a drain region forming a second homojunction with the channel region.
20. The method of claim 19 , wherein the drain region extends from the main surface plane to the semiconductor fin and comprises at least a drift zone forming the second homojunction and a drain contact zone, and wherein a maximum net dopant concentration in the drain contact zone is at least ten times as high as a mean net dopant concentration in the drift zone.