High voltage semiconductor device
A high voltage semiconductor device includes a semiconductor substrate, a first region, a second region, and an interconnection region. The first region includes an N-type first semiconductor region, an N-type drain region formed in the N-type first semiconductor region, a P-type first body region, an N-type source region formed in the P-type first body region, and a gate electrode formed between the N-type source region and the N-type drain region. The second region includes an N-type second semiconductor region, and a P-type second body region formed in the N-type second semiconductor region. The interconnection region is disposed between the first region and the second region, and includes a first insulation layer formed between the N-type first semiconductor region and the N-type second semiconductor region, a metal interconnection formed on the first insulation layer, and an isolation region formed in the substrate and disposed below the first insulation layer.
1. A high voltage semiconductor device, comprising:
a semiconductor substrate;
a first region formed in the semiconductor substrate, comprising:
an N-type first semiconductor region;
an N-type drain region formed in the N-type first semiconductor region;
a P-type first body region;
an N-type source region formed in the P-type first body region; and
a gate electrode formed between the N-type source region and the N-type drain region;
a second region formed in the semiconductor substrate, comprising:
an N-type second semiconductor region;
an N-type second well region formed in the N-type second semiconductor region; and
a P-type second body region formed in the N-type second semiconductor region; and
an interconnection region disposed between the first region and the second region, comprising:
a first insulation layer formed between the N-type first semiconductor region and the N-type second semiconductor region;
a metal interconnection formed on the first insulation layer; and
a P-type junction isolation region formed and disposed below the first insulation layer,
wherein the N-type second well region is in contact with the first insulation layer.
2. The high voltage semiconductor device of claim 1 , wherein the P-type junction isolation region has a same conductivity type as the semiconductor substrate and a higher doping concentration than a doping concentration of the semiconductor substrate.
3. The high voltage semiconductor device of claim 2 , wherein the P-type junction isolation region has a concentration over two orders of magnitude greater than a concentration of the semiconductor substrate.
4. The high voltage semiconductor device of claim 1 , further comprising:
an N-type first buried doping layer formed between the N-type first semiconductor region and the semiconductor substrate; and
an N-type second buried doping layer formed between the N-type second semiconductor region and the semiconductor substrate.
5. The high voltage semiconductor device of claim 1 , wherein the metal interconnection connects the N-type drain region to the P-type second body region.
6. The high voltage semiconductor device of claim 1 , wherein the second region further comprises:
a P-type first highly doped region and a P-type second highly doped region both formed in the P-type second body region;
a second insulation layer formed between the P-type first highly doped region and the P-type second highly doped region;
an N-type third highly doped region formed in the N-type second semiconductor region; and
a third insulation layer formed between the P-type second highly doped region and the N-type third highly doped region.
7. The high voltage semiconductor device of claim 6 , wherein the metal interconnection connects the N-type drain region to the P-type first highly doped region.
8. The high voltage semiconductor device of claim 1 , wherein the N-type second well region is disposed between the P-type junction isolation region and the P-type second body region.
9. A high voltage semiconductor device, comprising:
a semiconductor substrate;
a first region formed in the semiconductor substrate, comprising:
an N-type first semiconductor region;
an N-type drain region formed in the N-type first semiconductor region;
a P-type first body region;
an N-type source region formed in the P-type first body region;
a gate electrode formed between the N-type source region and the N-type drain region; and
a first deep trench formed adjacent to the P-type first body region;
a second region formed in the semiconductor substrate, comprising:
an N-type second semiconductor region;
an N-type second well region formed in the N-type second semiconductor region; and
a P-type second body region formed in the N-type second semiconductor region; and
an interconnection region disposed between the first region and the second region, comprising:
a first insulation layer formed between the N-type first semiconductor region and the N-type second semiconductor region; and
a metal interconnection formed on the first insulation layer,
wherein the N-type second well region is in contact with the first insulation layer, and
wherein second deep trenches are formed in the semiconductor substrate in contact with the first insulation layer.
10. The high voltage semiconductor device of claim 9 , wherein the first deep trench contacts the second deep trenches.
11. The high voltage semiconductor device of claim 9 , wherein the first deep trench and the second deep trenches are filled with an insulation film.
12. The high voltage semiconductor device of claim 9 , further comprising a P-type well region that encompasses the first deep trench.
13. A high voltage semiconductor device, comprising:
a first region comprising a Laterally Diffused Metal-Oxide-Semiconductor (LDMOS) device, the LDMOS device comprising:
an N-type high-concentration source region;
a P-type high-concentration pick-up region, wherein the N-type high-concentration source region and the P-type high-concentration pick-up region are formed in a first P-type body region;
a drain region;
a P-type buried doping layer formed below a bottom surface of an insulation layer; and
a P-type well region formed to partially encompass a first deep trench, and in contact with the first P-type body region;
a second region comprising:
a second body region;
a P-type first highly doped region and a P-type second highly doped region, wherein the P-type first highly doped region and the P-type second highly doped region are formed in the second body region;
a N-type third highly doped region; and
a second buried doping region; and
an interconnection region disposed between the first region and the second region.
14. The high voltage semiconductor device of claim 13 , wherein the interconnection region comprises a second deep trench.
15. The high voltage semiconductor device of claim 13 , wherein the first deep trench and a second deep trench surround the LDMOS device.
16. The high voltage semiconductor device of claim 15 , wherein the second deep trench comprises deep trenches.
17. The high voltage semiconductor device of claim 16 , wherein the deep trenches are formed between a first epitaxial layer and a second epitaxial layer.
18. The high voltage semiconductor device of claim 17 , wherein a metal interconnection connects the first region and the second region.
19. The high voltage semiconductor device of claim 13 , wherein the P-type well region has a depth greater than a depth of the first P-type body region, and less than a depth of the first deep trench.