IP Library Granted Patent US 10,566,713
Granted Patent B2
US 10,566,713 · App. 15/865,498 · Granted Feb 18, 2020

Press-fit power module and related methods

Inventors: Jie Chang (Suzhou SIP, CN); Huibin Chen (Suzhou SIP, CN); Tiburcio Maldo (Consolacion, PH); Keunhyuk Lee (Suzhou, CN)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01R12/585H01L23/49517H01L23/49541H01L23/49555H01L23/49579H01L23/49811H01R13/03H05K3/308H05K2201/1059
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Quick Facts
Patent No.
US 10,566,713
App. No.
15/865,498
Granted
Feb 18, 2020
Kind
B2
Abstract

Implementations of semiconductor packages may include: one or more die electrically coupled to a lead frame. The lead frame may be included within a housing. The semiconductor package may also include a set of signal leads extending from the housing, a set of power leads extending from the housing, and a plurality of press fit pins each fixedly coupled to the set of signal leads and the set of power leads. The set of signal leads and the set of power leads may be configured to couple with a substrate.

Claims (32)

1. A semiconductor package comprising:

one or more die electrically coupled to a leadframe; the leadframe comprised within a housing;

a set of signal leads extending from the housing;

a set of power leads extending from the housing opposite the set of signal leads; and

a plurality of press fit pins, each of the press fit pins welded, soldered, or brazed to the set of signal leads and the set of power leads in a straight orientation;

wherein the plurality of press fit pins are configured to couple with a circuit board.

2. The semiconductor package of claim 1 , wherein the semiconductor package is a power module.

3. The semiconductor package of claim 1 , wherein the plurality of press fit pins are coupled to the signal leads and the power leads through either one of welding, soldering, or brazing using a jig.

4. The semiconductor package of claim 1 , wherein the set of signal leads are on a first side of the housing and the set of power leads are on a second side of the housing opposing the first side.

5. The semiconductor package of claim 1 , wherein the leadframe comprises 99.9% purity copper.

6. The semiconductor package of claim 1 , wherein the plurality of press fit pins comprise a CuCrAgFeTiSi alloy.

7. A semiconductor package comprising:

a power module comprising:

a set of signal leads coupled to the power module;

a set of power leads coupled to the power module on a side of the power module opposing the set of signal leads; and

a press fit pin either one of welded, soldered, or brazed to each of the signal leads and to each of the power leads in a straight orientation;

wherein the press fit pin is configured to couple with a circuit board.

8. The semiconductor package of claim 7 , wherein the power module comprises one of a switch, a rectifier, or an inverter.

9. The semiconductor package of claim 7 , wherein the press fit pin is coupled to one of the set of signal leads and to one of the set of power leads through either one of welding, soldering, or brazing using a jig.

10. The semiconductor package of claim 7 , wherein the power module further comprises a leadframe comprising the set of signal leads and the set of power leads.

11. The semiconductor package of claim 10 , wherein the leadframe comprises 99.9% purity copper.

12. The semiconductor package of claim 7 , wherein the press fit pin comprises a CuCrAgFeTiSi alloy.

13. A semiconductor package comprising:

one or more die electrically coupled to a leadframe; the leadframe comprised within a housing;

a set of signal leads extending from the housing, wherein a first set of press-fit pins is coupled to an end of the set of signal leads;

a set of power leads extending from the housing on the opposite side of the housing from the set of signal leads, wherein a second set of press-fit pins is coupled to an end of the set of power leads;

wherein the first set press fit pins and the second set of press fit pins are configured to couple with a circuit board.

14. The semiconductor package of claim 13 , wherein the first set of press fit pins and the second set of press fits pins are either one of welded, soldered, or brazed to the set of signal leads and the set of power leads, respectively.

15. The semiconductor package of claim 13 , further comprising a power module.

16. The semiconductor package of claim 15 , wherein the power module comprises one of a switch, a rectifier, or an inverter.

17. The semiconductor package of claim 13 , wherein the leadframe comprises 99.9% purity copper.

18. The semiconductor package of claim 13 , wherein the first set of press fit pins and the second set of press fit pins each comprise a CuCrAgFeTiSi alloy.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 047734, FRAME 0068 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064160/0027 →
SECURITY INTEREST Recorded Dec 6, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047734/0068 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2018
From: CHANG, JIE; CHEN, HUIBIN; MALDO, TIBURCIO; LEE, KEUNHYUK
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 044571/0280 →