IP Library › Granted Patent US 10,509,169
Granted Patent B2
US 10,509,169 · App. 15/875,577 · Granted Dec 17, 2019

Semiconductor structure and manufacturing method of the same

Inventors: Yung-Chang Chang (Taipei, TW); Chung-Yen Chou (Hsinchu, TW); Ming-Chyi Liu (Hsinchu, TW); Shih-Chang Liu (Kaohsiung County, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
G02B6/136G02B6/124G02B6/1228G02B2006/12061G02B2006/12107
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Quick Facts
Patent No.
US 10,509,169
App. No.
15/875,577
Granted
Dec 17, 2019
Kind
B2
Abstract

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate and a gate element over the substrate. The gate element includes: a gate dielectric layer over the substrate; a gate electrode over the gate dielectric layer; and a waveguide passing through the gate electrode from a top surface of the gate electrode to a bottom surface of the gate electrode. A manufacturing method of the same is also disclosed.

Claims (40)

1. A semiconductor structure, comprising:

a gate element, the gate element including:

a gate dielectric layer;

a gate electrode over the gate dielectric layer;

a pair of spacers formed along sidewalls of the gate dielectric layer and the gate electrode; and

a waveguide passing through the gate electrode from a top surface of the gate electrode to a bottom surface of the gate electrode, the waveguide being directly adjacent to the gate electrode; and

a grating coupler structure beneath the waveguide.

2. The semiconductor structure of claim 1 , wherein the waveguide is filled with air.

3. The semiconductor structure of claim 1 , wherein the waveguide fully overlaps the grating coupler structure from a top view.

4. The semiconductor structure of claim 1 , wherein a bottom surface of the waveguide is isolated from the grating coupler by the gate dielectric layer.

5. The semiconductor structure of claim 1 , further comprising a contact etch stop layer covering a top surface of the gate electrode.

6. The semiconductor structure of claim 1 , wherein the gate electrode includes polysilicon.

7. The semiconductor structure of claim 1 , wherein the waveguide has a tapered structure.

8. The semiconductor structure of claim 1 , wherein the waveguide has a round bottom.

9. A semiconductor structure, comprising:

a substrate;

a grating coupler structure at least partially embedded in the substrate; and

a waveguide over the grating coupler; and

wherein a sidewall of the waveguide is encompassed by a gate element, and the gate element includes a gate dielectric layer, a gate electrode and a pair of spacers along sidewalls of the gate dielectric layer and the gate electrode.

10. The semiconductor structure of claim 9 , wherein the waveguide is filled with air.

11. The semiconductor structure of claim 9 , wherein the gate element includes:

a gate dielectric layer over the substrate;

a gate electrode over the gate dielectric layer; and

a silicon nitride layer over the gate electrode.

12. The semiconductor structure of claim 11 , wherein the sidewall of the waveguide is encompassed by the gate electrode of the gate element.

13. The semiconductor structure of claim 12 , wherein the sidewall of the waveguide is further encompassed by the silicon nitride layer of the gate element.

14. The semiconductor structure of claim 11 , wherein the waveguide is laminated on the gate dielectric layer.

15. The semiconductor structure of claim 14 , wherein a width of a bottom surface of the waveguide is narrower than a width of the gate dielectric layer.

16. The semiconductor structure of claim 11 , wherein the gate electrode includes polysilicon.

17. The semiconductor structure of claim 9 , further comprising an inter level dielectric (ILD) material including a metallization layer over the substrate.

18. The semiconductor structure of claim 17 , wherein the waveguide is further encompassed by the ILD material.

19. A method for manufacturing a semiconductor structure, comprising:

providing a semiconductor substrate;

forming a gate element over the semiconductor substrate, the gate element including a gate dielectric layer, a gate electrode over the gate dielectric layer and a pair of spacers along sidewalls of the gate dielectric layer and the gate electrode;

forming an inter level dielectric (ILD) material over the gate element;

performing a first etch to form an opening penetrating through the ILD material and stopping at the gate electrode; and

performing a second etch to expand the opening to penetrate through the gate electrode and stop at the gate dielectric layer.

20. The semiconductor structure of claim 19 , wherein the

providing the semiconductor substrate comprises:

providing the semiconductor substrate having a grating coupler structure therein.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2018
From: CHANG, YUNG-CHANG; CHOU, CHUNG-YEN; LIU, MING-CHYI; LIU, SHIH-CHANG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Reel/Frame 046841/0174 →
Continuity (2)
Provisional Application 62579046 · Oct 30, 2017
Related Publication 20190129098A1 · May 2, 2019
Cited By (1)
US 12,742,928