Semiconductor device and electronic device including the semiconductor device
A semiconductor device with a small circuit area that consumes low power is provided. The semiconductor device includes a shift register, a sample-and-hold circuit, a first buffer circuit, and a second buffer circuit. The sample-and-hold circuit includes a first input terminal, a second input terminal, and an output terminal. An output terminal of the first buffer circuit is electrically connected to the first input terminal. The shift register is electrically connected to the second input terminal. An input terminal of the second buffer circuit is electrically connected to the output terminal of the sample-and-hold circuit. In the semiconductor device, the potential of an input analog signal is retained in the sample-and-hold circuit and the analog signal is output from an output terminal of the second buffer circuit.
1. A semiconductor device comprising:
a shift register;
a sample-and-hold circuit;
a first demultiplexer;
a second demultiplexer;
a first buffer circuit; and
a second buffer circuit,
wherein the sample-and-hold circuit comprises a first input terminal, a second input terminal, and an output terminal,
wherein an output terminal of the first buffer circuit is electrically connected to the first input terminal of the sample-and-hold circuit,
wherein the shift register is electrically connected to the second input terminal of the sample-and-hold circuit,
wherein an input terminal of the second buffer circuit is electrically connected to the output terminal of the sample-and-hold circuit,
wherein the first demultiplexer is electrically connected to the output terminal of the first buffer circuit and the first input terminal of the sample-and-hold circuit,
wherein the second demultiplexer is electrically connected to the shift register and the second input terminal of the sample-and-hold circuit,
wherein an input terminal of the first buffer circuit is configured to receive an analog signal, and
wherein the sample-and-hold circuit is configured to receive the analog signal through the first input terminal when a signal from the shift register is transmitted to the second input terminal and is configured to hold a potential corresponding to the analog signal.
2. The semiconductor device according to claim 1 , wherein the sample-and-hold circuit further comprises a first transistor and a first capacitor.
3. The semiconductor device according to claim 2 ,
wherein a first terminal of the first transistor is electrically connected to the first input terminal,
wherein a second terminal of the first transistor is electrically connected to the output terminal of the sample-and-hold circuit,
wherein a gate of the first transistor is electrically connected to the second input terminal, and
wherein a first terminal of the first capacitor is electrically connected to the second terminal of the first transistor.
4. The semiconductor device according to claim 2 , wherein the first transistor comprises a metal oxide in a channel formation region.
5. The semiconductor device according to claim 2 , further comprising a display portion,
wherein the display portion comprises a second transistor in a pixel, and
wherein the second transistor comprises hydrogenated amorphous silicon in a channel formation region.
6. The semiconductor device according to claim 2 , further comprising a display portion,
wherein the display portion comprises a second transistor in a pixel, and
wherein the second transistor comprises a metal oxide in a channel formation region.
7. The semiconductor device according to claim 1 , further comprising an autoencoder,
wherein the autoencoder is electrically connected to the input terminal of the first buffer circuit,
wherein the autoencoder is configured to convert first image data into second image data obtained by feature extraction of the first image data, restore the second image data into the first image data, and output the first image data restored as the analog signal, when a first analog signal based on the first image data is input to the autoencoder, and
wherein the analog signal is input to the input terminal of the first buffer circuit.
8. The semiconductor device according to claim 7 ,
wherein the autoencoder comprises an encoder and a decoder,
wherein the encoder is configured to convert first image data into second image data by feature extraction and output the second image data to the decoder, and
wherein the decoder is configured to restore the second image data into the first image data and output the first image data.
9. The semiconductor device according to claim 8 ,
wherein the encoder comprises a neural network configured to perform convolution using a weight filter.
10. A semiconductor device comprising:
a shift register;
a first demultiplexer;
a second demultiplexer;
a sample-and-hold circuit;
a first buffer circuit; and
a second buffer circuit,
wherein the sample-and-hold circuit comprises a first input terminal, a second input terminal, and an output terminal,
wherein an output terminal of the first buffer circuit is electrically connected to an input terminal of the first demultiplexer,
wherein an output terminal of the first demultiplexer is electrically connected to the first input terminal,
wherein the shift register is electrically connected to an input terminal of the second demultiplexer,
wherein an output terminal of the second demultiplexer is electrically connected to the second input terminal,
wherein an input terminal of the second buffer circuit is electrically connected to the output terminal of the sample-and-hold circuit, and
wherein the sample-and-hold circuit is configured to receive an analog signal through the first input terminal when a signal from the shift register is transmitted to the second input terminal and is configured to hold a potential corresponding to the analog signal.
11. The semiconductor device according to claim 10 , wherein the first demultiplexer and the second demultiplexer are controlled by the same signal.
12. The semiconductor device according to claim 10 , wherein the sample-and-hold circuit further comprises a first transistor and a first capacitor.
13. The semiconductor device according to claim 12 ,
wherein a first terminal of the first transistor is electrically connected to the first input terminal,
wherein a second terminal of the first transistor is electrically connected to the output terminal of the sample-and-hold circuit,
wherein a gate of the first transistor is electrically connected to the second input terminal, and
wherein a first terminal of the first capacitor is electrically connected to the second terminal of the first transistor.
14. The semiconductor device according to claim 12 , wherein the first transistor comprises a metal oxide in a channel formation region.
15. The semiconductor device according to claim 12 , further comprising a display portion,
wherein the display portion comprises a second transistor in a pixel, and
wherein the second transistor comprises hydrogenated amorphous silicon in a channel formation region.
16. The semiconductor device according to claim 12 , further comprising a display portion,
wherein the display portion comprises a second transistor in a pixel, and
wherein the second transistor comprises a metal oxide in a channel formation region.
17. The semiconductor device according to claim 10 , further comprising an autoencoder,
wherein the autoencoder is electrically connected to an input terminal of the first buffer circuit in the semiconductor device,
wherein the autoencoder is configured to convert first image data into second image data obtained by feature extraction of the first image data, restore the second image data into the first image data, and output the first image data restored as a second analog signal, when a first analog signal based on the first image data is input to the autoencoder, and
wherein the second analog signal is input to the input terminal of the first buffer circuit.