Granted Patent B2

US 12,389,608 · App. 18/391,970 · Granted Aug 12, 2025

Inventors: Hajime Kimura (Atsugi, JP); Yoshiyuki Kurokawa (Sagamihara, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

H10B61/20H03K19/20H10B61/10H10B63/30

Abstract

Claims (25)

1. A semiconductor device comprising a first circuit and a second circuit,

wherein the first circuit comprises first to fourth transistors, a ninth transistor, and a first capacitor,

wherein the second circuit comprises fifth to eight transistors, a tenth transistor, and a second capacitor,

wherein a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor, a gate of the ninth transistor, and a first terminal of the first capacitor,

wherein one of a source and a drain of the second transistor is electrically connected to a second terminal of the first capacitor and one of a source and a drain of the ninth transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein a gate of the third transistor is electrically connected to a first input wiring,

wherein a gate of the fourth transistor is electrically connected to a second input wiring,

wherein the other of the source and the drain of the third transistor is electrically connected to a first wiring,

wherein the other of the source and the drain of the ninth transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the other of the source and the drain of the fourth transistor is electrically connected to a second wiring,

wherein a gate of the sixth transistor is electrically connected to one of a source and a drain of the fifth transistor, a gate of the tenth transistor, and a first terminal of the second capacitor,

wherein one of a source and a drain of the sixth transistor is electrically connected to a second terminal of the second capacitor, and one of a source and a drain of the tenth transistor,

wherein the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor,

wherein a gate of the seventh transistor is electrically connected to the first input wiring,

wherein a gate of the eighth transistor is electrically connected to the second input wiring,

wherein the other of the source and the drain of the seventh transistor is electrically connected to the second wiring, and

wherein the other of the source and the drain of the eighth transistor is electrically connected to the first wiring.

2. The semiconductor device according to claim 1 ,

wherein the first circuit is configured to hold a first potential corresponding to first data at the gate of the second transistor,

wherein the second circuit is configured to hold a second potential corresponding to the first data at the gate of the sixth transistor,

wherein the first circuit is configured to output a current corresponding to the first potential to the first wiring, output a current corresponding to the first potential to the second wiring, and not output a current corresponding to the first wiring and the second wiring, and

wherein the second circuit is configured to output a current corresponding to the first potential to the second wiring, output a current corresponding to the second potential to the first wiring, and not output a current corresponding to the first wiring and the second wiring.

3. The semiconductor device according to claim 1 , wherein arithmetic operation of a neural network is performed by the semiconductor device.

4. The semiconductor device according to claim 2 , wherein arithmetic operation of a neural network is performed by the semiconductor device.

Priority Claims (2)

Continuity (3)

References Cited (50)