Internal circuit TMS input, FIFO coupled to parallel-input serial-output register
The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.
1. A debug interface of an integrated circuit comprising:
(a) a TCK input pin;
(b) a TDI input pin;
(c) a TDO output pin;
(d) a TMS inout pin; and
(e) a parallel-input serial-output register coupled to the TMS inout pin, (f) wherein the TMS inout pin is configured as an input pin for a mode signal of an IEEE1149.1 protocol when the debug interface is configured to a first mode to support the IEEE1149.1 protocol; and
(g) the TMS inout pin is configured as an output pin for read data signal for debug operation when the debug interface is configured to a second mode during which the read data signal is provided from an internal circuit in parallel to the parallel-input serial-output register and output serially from the parallel-input serial-output register at the TMS inout pin, the internal circuit including a FIFO coupled to the parallel-input serial-output register, wherein a parallel data is provided from the FIFO to the parallel-input serial-output register.
2. The debug interface of an integrated circuit of claim 1 , wherein the TMS inout pin is configured as an input pin for write data signal for debug operation when the debug interface is configured to a third mode during which the write data signal is input to the debug interface serially from the TMS inout pin.
3. The debug interface of an integrated circuit of claim 2 in which the IEEE1149.1 protocol includes a Test Logic Reset state, a Run Test/Idle state, a Select-DR state, and a Select-IR state.
4. The debug interface of an integrated circuit of claim 2 including a state machine coupled to the TCK input pin and the TMS inout pin and providing a Test Logic Reset state, a Run Test/Idle state, a Select-DR state, and a Select-IR state in response to clock signals on the TCK input pin and the mode signal on the TMS inout pin.
5. The debug interface of an integrated circuit of claim 2 in which the integrated circuit includes a core circuit coupled to the parallel-input serial-output register.
6. The debug interface of an integrated circuit of claim 2 including:
(a) access port circuitry coupled to the TCK input pin, the TDI input pin, the TDO output pin, and the TMS inout pin and including controller circuitry operable according to IEEE1149.1 protocol and coupled to the TMS inout pin and the TCK input pin, an instruction register connected to the TDI input pin, and a data register connected to the TDI input pin; and
(b) serial communication circuitry separate from the access port circuitry, the serial communication circuitry being coupled to the TMS inout pin to input data serially from the TMS inout pin and to output data serially to the TMS pin.
7. The debug interface of an integrated circuit of claim 6 in which the serial communication circuitry includes a counter operable to store a number of parallel data, wherein the parallel data comprises a plurality of data bits.
8. The debug interface of an integrated circuit of claim 7 in which the access port circuitry includes multiplexer circuitry coupling the instruction register and the data register to the TDO output pin.
9. The debug interface of an integrated circuit of claim 7 in which the instruction register has bus leads for updating and outputting data to other circuits and for capturing data from other circuits.
10. The debug interface of an integrated circuit of claim 7 in which the data register has bus leads for updating and outputting data to other circuits and for capturing data from other circuits.
11. The debug interface of an integrated circuit of claim 7 in which the access port circuitry includes state machine circuitry having four state output bits defining sixteen states.
12. The debug interface of an integrated circuit of claim 7 in which the access port circuitry includes state machine circuitry having four state output bits defining sixteen states that include a Test Logic Reset state, a Run Test/Idle state, a Select-DR state, and a Select-IR state.
13. The debug interface of an integrated circuit of claim 2 in which the integrated circuit includes core circuitry having data destination circuitry and data source circuitry, and including:
(a) communication circuitry having data input circuitry coupled to the TMS inout pin and the data destination circuitry and data output circuitry coupled to the data source circuitry and the TMS inout pin; and
(b) access port circuitry separate from the communication circuitry having a mode select input coupled to the TMS inout pin and a clock input coupled to the TCK input pin, the access port circuitry including state machine circuitry connected to the mode select input and the clock input and having control outputs, the access port circuitry including an instruction register and a data register connected to the control outputs of the state machine circuitry.
14. The debug interface of an integrated circuit of claim 13 in which the data destination circuitry includes any one of an address bus, a data bus, a Rain memory, a Cache memory, a register file, a FIFO, a register, a processor, a peripheral circuit, and a bus coupled to circuitry external to the IC.
15. The debug interface of an integrated circuit of claim 13 in which the data source circuitry includes any one of an address bus, a data bus, a Rain memory, a Cache memory, a register file, a FIFO, a register, a processor, a peripheral circuit, and a bus coupled to circuitry external to the IC.
16. The debug interface of an integrated circuit of claim 13 in which the data input circuitry includes a serial-input parallel-output register.
17. The debug interface of an integrated circuit of claim 13 in which the data output circuitry includes the parallel-input serial-output register.
18. The debug interface of an integrated circuit of claim 13 in which the data destination circuitry is separate from the data source circuitry.