VIA structure and methods of forming the same

1. A method, comprising:

providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view;

depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column;

depositing a hard mask layer over the sacrificial layer;

removing a portion of the hard mask layer from a bottom of the dip;

etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and

forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.

2. The method of claim 1 , wherein each of the plurality of sacrificial blocks has a cylinder shape.

3. The method of claim 2 , wherein the sacrificial layer includes the same material composition as the plurality of sacrificial blocks.

4. The method of claim 2 , wherein the sacrificial layer and the plurality of sacrificial blocks include different material compositions.

5. The method of claim 1 , wherein the plurality of sacrificial blocks consists of four sacrificial blocks.

6. The method of claim 1 , wherein the depositing of the hard mask layer includes performing a chemical vapor deposition (CVD) process.

7. The method of claim 1 , wherein the removing of the portion of the hard mask layer includes performing a wet etching process.

8. The method of claim 1 , wherein the forming of the conductive material inside the dip includes performing an atomic layer deposition (ALD) process.

9. The method of claim 1 , wherein the conductive material inside the dip includes titanium nitride.

10. The method of claim 1 , wherein the hard mask layer includes the same material composition as the conductive material inside the dip.

11. The method of claim 1 , further comprising:

performing a chemical-mechanical planarization (CMP) process to expose a top surface of the dielectric layer after the forming of the conductive material inside the dip.

12. The method of claim 11 , wherein the conductive material inside the dip has a width-to-height ratio less than 1.0, after the performing of the CMP process.

13. A method of forming a semiconductor device, comprising:

providing a semiconductor substrate having a bottom electrode;

forming a chemical-mechanical planarization (CMP) stop layer above the semiconductor substrate;

forming a first sacrificial layer above the CMP stop layer;

patterning the first sacrificial layer to form multiple sacrificial blocks around the bottom electrode from a top view;

depositing a second sacrificial layer over the multiple sacrificial blocks, wherein the second sacrificial layer has a dip directly above the bottom electrode;

removing a portion of the second sacrificial layer from a bottom of the dip, thereby exposing the CMP stop layer at the bottom of the dip;

etching the CMP stop layer through the bottom of the dip, thereby forming a via hole in the CMP stop layer; and

filling the via hole with a conductive material, wherein the conductive material is in physical contact with the bottom electrode.

14. The method of claim 13 , wherein the removing of the portion of the second sacrificial layer from the bottom of the dip includes:

forming a hard mask layer over the second sacrificial layer;

removing a portion of the hard mask layer above the bottom of the dip to expose the portion of the second sacrificial layer; and

etching the second sacrificial layer using the hard mask layer as an etching mask.

15. The method of claim 14 , wherein the forming of the hard mask layer includes depositing the hard mask layer with a smaller thickness at the bottom of the dip than on sidewalls of the dip.

16. The method of claim 13 , after the filling of the via hole with the conductive material, further comprising:

performing a CMP process to remove the second sacrificial layer and the multiple sacrificial blocks;

forming a phase-change material layer over the CMP stop layer, wherein the phase-change material layer is in physical contact with the conductive material; and

forming a top electrode above the phase-change material layer.

17. The method of claim 16 , wherein the phase-change material layer includes GeSbTe, AgInSbTe, or hafnium oxide.

18. A method, comprising:

providing a substrate having an electrode embedded in the substrate;

forming a plurality of dielectric blocks above the electrode, wherein the plurality of dielectric blocks surrounds the electrode from a top view;

depositing a sacrificial layer covering top and sidewall surfaces of the plurality of dielectric blocks, wherein the sacrificial layer has a dip directly above the electrode;

etching through a bottom of the dip to expose a top surface of the electrode; and

depositing a conductive material in the dip, wherein the conductive material is in physical contact with the electrode.

19. The method of claim 18 , wherein the forming of the plurality of dielectric blocks includes:

forming a dielectric layer covering the substrate and the electrode; and

patterning the dielectric layer to form the plurality of dielectric blocks.

20. The method of claim 18 , further comprising:

performing a chemical-mechanical planarization (CMP) process to remove the plurality of dielectric blocks and the sacrificial layer.