Via structure and methods of forming the same
A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.
1. A semiconductor device, comprising:
a substrate;
a bottom electrode in the substrate;
a dielectric layer over the bottom electrode and the substrate;
a conductive via through the dielectric layer, the conductive via extending to the bottom electrode and having a width-to-height ratio less than 1.0;
a chalcogenide glass layer over the conductive via; and
a top electrode over the chalcogenide glass layer,
wherein top surfaces of the bottom electrode and the substrate are coplanar.
2. The semiconductor device of claim 1 , wherein the width-to-height ratio of the conductive via is within a range from about 0.2 to about 1.0.
3. The semiconductor device of claim 1 , wherein the dielectric layer includes silicon carbide and the conductive via includes titanium nitride.
4. The semiconductor device of claim 1 , wherein the substrate comprises silicon, silicon germanium, or gallium arsenide.
5. The semiconductor device of claim 1 , wherein the bottom electrode comprises tungsten, aluminum, copper, or aluminum copper.
6. The semiconductor device of claim 1 , wherein the top electrode comprises titanium nitride or tantalum nitride.
7. The semiconductor device of claim 1 , wherein a height of the conductive via is between about 20 nm and about 100 nm.
8. A semiconductor device, comprising:
a semiconductor substrate;
a bottom electrode in the semiconductor substrate;
a first dielectric layer extending along and interfacing top surfaces of the bottom electrode and the semiconductor substrate;
a conductive via through the first dielectric layer to couple to the bottom electrode;
a phase-change layer over the conductive via; and
a top electrode over the phase-change layer,
wherein the phase-change layer comprises a GeSbTe alloy, an AgInSbTe alloy, or a hafnium oxide compound.
9. The semiconductor device of claim 8 , wherein the conductive via comprises a width-to-height ratio less than 1.0.
10. The semiconductor device of claim 9 , wherein the width-to-height ratio of the conductive via is within a range from about 0.2 to about 1.0.
11. The semiconductor device of claim 8 , further comprising:
a second dielectric layer over the first dielectric layer and the top electrode.
12. The semiconductor device of claim 11 , wherein the first dielectric layer and the second dielectric layer comprise silicon nitride.
13. The semiconductor device of claim 11 , further comprising:
a metal via disposed over the top electrode; and
a metal line disposed over the metal via.
14. The semiconductor device of claim 13 , wherein the phase-change layer, the top electrode, the metal via, and the metal line are disposed in the second dielectric layer.
15. The semiconductor device of claim 14 , wherein the metal via and the metal line comprise aluminum, copper, aluminum copper, or tungsten.
16. A semiconductor structure, comprising:
a semiconductor substrate comprising a memory region and a peripheral region;
a conductive feature disposed in the semiconductor substrate in the peripheral region;
a bottom electrode disposed in the semiconductor substrate in memory region;
a first dielectric layer over the semiconductor substrate;
a second dielectric layer over the first dielectric layer;
a conductive via extending through the first dielectric layer to couple to the bottom electrode;
a phase-change layer disposed in the second dielectric layer and over the conductive via;
a top electrode disposed in the second dielectric layer and over the phase-change layer; and
a metal via extending through the second dielectric layer and the first dielectric layer to couple to the conductive feature in the peripheral region.
17. The semiconductor structure of claim 16 , wherein the phase-change layer comprises a GeSbTe alloy, an AgInSbTe alloy, or a hafnium oxide compound.
18. The semiconductor structure of claim 16 , wherein the semiconductor substrate comprises silicon, silicon germanium, or gallium arsenide.
19. The semiconductor structure of claim 16 , wherein the conductive via comprises a width-to-height ratio less than 1.0.
20. The semiconductor structure of claim 16 , wherein the first dielectric layer and the second dielectric layer comprise silicon nitride.