Method for producing a semiconductor package
An object of the present invention is to provide a semiconductor package with which it is possible to reduce a volume of an encapsulation resin and to easily embed a resin regardless of thicknesses of semiconductor chips and a small distance between adjacent semiconductor chips, as well as to provide a thin semiconductor package with which a final product includes no support flat plate. To realize this, a semiconductor package having a structure wherein semiconductor chips are accommodated in cavity parts of a support which is formed by copper plating and includes the cavity parts is provided.
1. A method for producing a semiconductor package, including, in the following order, the steps of:
laying a copper foil on one main face of a support flat plate;
performing electroplating to form a copper plating layer on the copper foil;
performing electroplating to form cavity parts on the copper plating layer;
fixing surfaces opposite to element circuit surfaces of semiconductor chips in the cavity parts with an adhesive;
resin-encapsulating the semiconductor chips with an insulating resin to form an encapsulation resin layer;
forming openings in the insulating material layer upon positions corresponding to electrodes arranged on the element circuit surfaces of the semiconductor chips;
forming, on the insulating material layer, wiring layers partially extended to peripheral regions of the semiconductor chips, and forming, in the openings of the insulating material layer, conductive parts connected to the electrodes of the semiconductor chips;
forming a solder resist on the wiring layer except in portions corresponding to the openings;
forming external electrodes on parts of the wiring layer corresponding to the openings;
separating the support flat plate from the copper foil; and
forming an insulating material layer on the copper foil after separation.
2. The method for producing a semiconductor package according to claim 1 , wherein
the cavity parts are formed by forming parts that are not copper-plated by pattern plating using a resist.
3. A method for producing a semiconductor package having a support flat plate, including, in the following order, the steps of:
laying a copper foil on one main face of the support flat plate;
performing electroplating to form a copper plating layer on the copper foil;
performing electroplating to form cavity parts on the copper plating layer;
fixing surfaces opposite to element circuit surfaces of semiconductor chips in the cavity parts with an adhesive;
resin-encapsulating the semiconductor chips with an insulating resin to form an encapsulation resin layer;
forming openings in the insulating material layer upon positions corresponding to electrodes arranged on the element circuit surfaces of the semiconductor chips;
forming, on the insulating material layer, wiring layers partially extended to peripheral regions of the semiconductor chips, and forming, in the openings of the insulating material layer, conductive parts connected to the electrodes of the semiconductor chips;
forming a solder resist on the wiring layer except in portions corresponding to the openings; and
forming external electrodes on parts of the wiring layer corresponding to the openings.
4. The method for producing a semiconductor package according to claim 3 , wherein
the cavity parts are formed by forming parts that are not copper-plated by pattern plating using a resist.
5. A method for producing a semiconductor package, including, in the following order, the steps of:
laying a copper foil on each of both surfaces of a support flat plate;
performing electroplating to form a copper plating layer on the copper foil;
performing electroplating to form cavity parts on the copper plating layer;
fixing surfaces opposite to element circuit surfaces of semiconductor chips in the cavity parts with an adhesive;
resin-encapsulating the semiconductor chips with an insulating resin to form an encapsulation resin layer;
forming openings in the insulating material layer upon positions corresponding to electrodes arranged on the element circuit surfaces of the semiconductor chips;
forming, on the insulating material layer, wiring layers partially extended to peripheral regions of the semiconductor chips, and forming, in the openings of the insulating material layer, conductive parts connected to the electrodes of the semiconductor chips;
forming a solder resist on the wiring layer except in portions corresponding to the openings;
forming external electrodes on parts of the wiring layer corresponding to the openings
to form package parts on both surfaces of the support flat plate;
separating the support flat plate from the copper foils of the package parts to obtain two package parts; and
forming an insulating material layer on the copper foils of the two package parts.