Semiconductor device including buried capacitive structures and a method of forming the same

1. A method, comprising:

forming a plurality of openings extending through a semiconductor layer, through a buried insulating layer, and into a substrate material in a second device region of a semiconductor device while covering a first device region of said semiconductor device;

forming an insulating material on sidewalls and on a bottom face of each of said plurality of openings; and

forming a first capacitor electrode in each of said plurality of openings in the presence of said insulating material, wherein each of said first capacitor electrodes comprises a conductive material and partially fills a respective one of said plurality of openings.

2. The method of claim 1 , further comprising forming trench isolation structures extending through said semiconductor layer, through said buried insulating layer, and into said substrate material, said trench isolation structures laterally delineating and separating said first and second device regions.

3. The method of claim 2 , wherein said trench isolation structures are formed after forming said first capacitor electrodes.

4. The method of claim 1 , further comprising forming a recess in said second device region so as to expose said substrate material.

5. The method of claim 4 , further comprising forming a contact element that is conductively coupled to said substrate material exposed by said recess in said second device region, said contact element providing an electrical connection to a second capacitor electrode formed in a portion of said substrate material below each of said first capacitor electrodes.

6. The method of claim 5 , wherein said second capacitor electrode is a shared capacitor electrode of each of said first capacitor electrodes.

7. The method of claim 1 , further comprising performing a common processing sequence to form a gate electrode of a transistor element above said first device region and a plurality of electrode lines above said second device region.

8. The method of claim 1 , wherein forming said insulating material on said sidewalls and on said bottom face of each of said plurality of openings comprises:

forming a layer of insulating material in each of said plurality of openings, a bottom portion of said layer of insulating material covering said bottom face of each of said plurality of openings; and

reducing a thickness of said bottom portion of said layer of insulating material in each of said plurality of openings, said reduced thickness bottom portion covering said bottom face of each of said plurality of openings.

9. The method of claim 1 , wherein forming said insulating material on said sidewalls and on said bottom face of each of said plurality of openings comprises:

forming a first layer of insulating material in each of said plurality of openings, a bottom portion of said first layer of insulating material covering said bottom face of each of said plurality of openings;

completely removing said bottom portion of said first layer of insulating material from each of said plurality of openings; and

forming a second layer of insulating material in each of said plurality of openings, a bottom portion of said second layer of insulating material re-covering said bottom face of each of said plurality of openings.

10. The method of claim 1 , wherein forming said first capacitor electrode in each of said plurality of openings comprises:

forming a layer of said conductive material so as to overfill each of said plurality of openings;

performing a planarization process to remove portions of said layer of said conductive material formed outside of said plurality of openings; and

removing a portion of said conductive material from each of said plurality of openings by performing an etch process.

11. A method, comprising:

forming a plurality of openings extending through a semiconductor layer, through a buried insulating layer, and into a substrate material in a second device region of a semiconductor device while covering a first device region of said semiconductor device;

forming an insulating material in each of said plurality of openings, said insulating material covering sidewalls and a bottom face of each of said plurality of openings;

forming a first capacitor electrode comprising a conductive material in each of said plurality of openings, said insulating material separating said first capacitor electrodes from said sidewalls and said bottom faces of said plurality of openings, wherein a height level of a top surface of each of said first capacitor electrodes is positioned at or below a height level of a bottom face of said semiconductor layer; and

forming an electrical connection to a second capacitor electrode formed in a portion of said substrate material in said second device region below each of said first capacitor electrodes, wherein said second capacitor electrode is a shared capacitor electrode of each of said first capacitor electrodes.

12. The method of claim 11 , wherein forming said electrical connection to said second capacitor electrode comprises:

forming a recess in said second device region so as to expose said substrate material; and

forming a contact element that is conductively coupled to said substrate material exposed by said recess in said second device region.

13. The method of claim 11 , further comprising forming trench isolation structures extending through said semiconductor layer, through said buried insulating layer, and into said substrate material, said trench isolation structures laterally delineating and separating said first and second device regions.

14. The method of claim 13 , wherein said trench isolation structures are formed after forming said first capacitor electrodes.

15. The method of claim 11 , further comprising performing a common processing sequence to form a gate electrode of a transistor element above said first device region and a plurality of electrode lines above said second device region.

16. The method of claim 11 , wherein forming said insulating material in each of said plurality of openings comprises:

forming a layer of insulating material in each of said plurality of openings, a bottom portion of said layer of insulating material covering said bottom face of each of said plurality of openings; and

reducing a thickness of said bottom portion of said layer of insulating material in each of said plurality of openings, said reduced thickness bottom portion covering said bottom face of each of said plurality of openings.

17. The method of claim 11 , wherein forming said insulating material in each of said plurality of openings comprises:

forming a first layer of insulating material in each of said plurality of openings, a bottom portion of said first layer of insulating material covering said bottom face of each of said plurality of openings;

completely removing said bottom portion of said first layer of insulating material from each of said plurality of openings; and

forming a second layer of insulating material in each of said plurality of openings, a bottom portion of said second layer of insulating material re-covering said bottom face of each of said plurality of openings.

18. The method of claim 11 , wherein forming said first capacitor electrode in each of said plurality of openings comprises:

forming a layer of said conductive material in each of said plurality of openings; and

performing an etch process to remove a portion of said conductive material from each of said plurality of openings.

19. The method of claim 11 , wherein forming said first capacitor electrode in each of said plurality of openings comprises:

forming a layer of said conductive material above said second device region, said layer of conductive material overfilling each of said plurality of openings;

performing a planarization process to remove portions of said layer of said conductive material formed outside of said plurality of openings; and

performing an etch process to remove a portion of said conductive material from each of said plurality of openings.