IP Library Granted Patent US 11,025,038
Granted Patent B2
US 11,025,038 · App. 15/891,474 · Granted Jun 1, 2021

Methods and apparatus for a current circuit

Inventor: Yasuhiro Nodake (Oizumi-machi, JP)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01T15/00F02P7/077G01R19/0092H03K3/01
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Quick Facts
Patent No.
US 11,025,038
App. No.
15/891,474
Granted
Jun 1, 2021
Kind
B2
Abstract

Various embodiments of the present technology comprise a method and apparatus for a current circuit. According to various embodiments, the current circuit may be utilized for current detection or current limiting. The current circuit may be configured to compensate for a base current, making detection of an input current more accurate.

Claims (74)

1. A current circuit capable of generating a base current, comprising:

a first current mirror circuit;

a current source connected to the first current mirror circuit and configured to generate a source current;

a second current mirror circuit connected to the first current mirror circuit;

an input circuit comprising:

a first transistor; and

a second transistor;

wherein a base terminal of the first transistor is connected to a base terminal of the second transistor at a first node; and

a current compensation circuit connected between the first node and the second current mirror circuit;

wherein the current detection circuit outputs a detection signal based on a load current.

2. The current circuit according to claim 1 , wherein the first current mirror circuit comprises a plurality of transistor configured as a cascoded current mirror circuit.

3. The current circuit according to claim 1 , wherein the current compensation circuit is further connected to the first current mirror circuit.

4. The current circuit according to claim 1 , wherein the input circuit further comprises:

a reference resistor coupled to the first transistor; and

a sense resistor coupled to the second transistor.

5. The current circuit according to claim 1 , wherein the detection signal is independent of the base current.

6. The current circuit according to claim 5 , the current compensation transistor generates a current equal to twice the base current.

7. The current circuit according to claim 1 , wherein the detection signal is independent of a temperature of the current detection circuit.

8. The current circuit according to claim 1 , wherein the input circuit is further connected to the first current mirror circuit via a first connection and a second connection.

9. The current circuit according to claim 1 , wherein:

the first current mirror circuit is configured to supply a first current to the input circuit, wherein the first current is equal to the source current minus the base current; and

the current compensation transistor is configured to supply a second current to the input circuit, wherein the second current is equal to twice the base current to the input circuit.

10. The current circuit according to claim 1 , wherein:

the first current mirror circuit is configured to supply a first current to the input circuit, wherein the first current is equal to a first transistor factor multiplied by the source current minus the base current; and

the current compensation transistor is configured to supply a second current to the input circuit, wherein the second current is equal to a sum of the first transistor factor and a second transistor factor multiplied by the base current.

11. A method for detecting a load current, comprising:

receiving the load current;

providing a source current;

generating a base current;

compensating for the base current; and

generating a detection signal according to the load current;

wherein the detection signal is independent of:

the base current; and

a change in temperature.

12. The method according to claim 11 , wherein compensating for the base current comprises:

generating a first current proportional to a first transistor factor plus a second transistor factor;

generating a second current proportional to the first transistor factor;

generating a third current proportional to the second transistor factor; and

splitting the first current into two currents, wherein one of the split currents is proportional to the first transistor factor and the remaining split current is proportional to the second transistor factor.

13. The method according to claim 11 , wherein generating the detection signal comprises:

generating a first voltage potential that is proportional to the load current; and

comparing the first voltage potential to a second voltage potential.

14. The method according to claim 11 , wherein:

the detection signal comprises a digital signal; and

generating the detection signal comprises switching to one of a high signal and a low signal when the load current reaches a predetermined threshold.

15. The method according to claim 14 , wherein the predetermined threshold is fixed across a plurality of operating temperatures and a plurality of hybrid parameter forward current gain values.

16. A system, comprising:

a load configured to generate a load current;

an igniter, connected to the load and configured to detect the load current, comprising:

an operational amplifier comprising:

a cascoded current mirror circuit;

a current splitting circuit connected to the cascoded current mirror circuit;

an input circuit configured to detect the load current and comprising:

a bipolar first transistor; and

a second bipolar transistor connected to the first bipolar transistor;

wherein first transistor and the second transistor share a base terminal; and

a current compensation transistor connected between the base terminal and the second current mirror circuit;

a sense resistor connected to a first terminal of the operational amplifier; and

a reference resistor connected to a second terminal of the operational amplifier;

wherein the igniter outputs a detection signal based on the load current.

17. The system according to claim 16 , wherein the current compensation transistor: is further connected to the first current mirror circuit;

comprises a bipolar transistor; and

is configured to generate an emitter current equal to twice the base current of the input circuit.

18. The system according to claim 16 , wherein:

the input circuit is further connected to the cascoded current mirror circuit via a first connection and a second connection; and

the cascoded current mirror circuit is configured to supply:

a first current through the first connection, wherein the first current is equal to the source current minus a base current; and

a second current through the second connection, wherein the second current is equal to the source current minus the base current.

19. The system according to claim 16 , wherein detection signal is independent of a base current of the input circuit.

20. The system according to claim 16 , wherein:

the current splitting circuit is connected to the cascoded current mirror circuit via a third connection and a fourth connection; and

the cascoded current mirror circuit is configured to supply:

a third current through the third connection, wherein the third current is equal to the base current; and

a fourth current through the fourth connection, wherein the fourth current is equal to the base current.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 047734, FRAME 0068 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064160/0027 →
SECURITY INTEREST Recorded Dec 6, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047734/0068 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2018
From: NODAKE, YASUHIRO
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 044991/0249 →
Continuity (1)
Related Publication 20190245328A1 · Aug 8, 2019