FinFET-based ESD devices and methods for forming the same
A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.
1. A semiconductor device comprising:
an electrostatic discharge device surrounded by a pick-up device, wherein the electrostatic discharge device comprises:
a first fin of semiconductor material over a semiconductor substrate;
a second fin of semiconductor material over the semiconductor substrate;
a first gate electrode over the first fin and the second fin;
a second gate electrode over the first fin and the second fin;
a drain region extending from the first gate electrode to the second gate electrode, wherein the drain region has a merged drain epitaxy region and a non-merged drain epitaxy region.
2. The semiconductor device of claim 1 , wherein the first fin and the second fin are part of an array of fins.
3. The semiconductor device of claim 1 , wherein the pick-up device comprises at least one highly doped well with a first conductivity, wherein the semiconductor substrate below the pick-up device has the first conductivity.
4. The semiconductor device of claim 3 , further comprising a dummy gate structure over the at least one highly doped well.
5. The semiconductor device of claim 3 , wherein the at least one highly doped well comprises an epitaxy region.
6. The semiconductor device of claim 5 , further comprising a silicide region on the epitaxy region.
7. A semiconductor device comprising:
a pick-up device encircling a first region of a semiconductor substrate in a top-down view; and
an electrostatic discharge device located within the first region, wherein the electrostatic discharge device comprises:
a first fin of semiconductor material over the semiconductor substrate;
a second fin of semiconductor material over the semiconductor substrate:
a first isolation region between the first fin and the second fin;
a first gate electrode over the first fin and the second fin;
a second gate electrode over the first fin and the second fin;
a drain region extending from the first gate electrode to the second gate electrode and extending from the first fin to the second fin; and
a depression within the drain region, wherein the depression has a curved surface and exposes the first isolation region.
8. The semiconductor device of claim 7 , wherein the pick-up device comprises one or more highly doped wells with a first conductivity and wherein the semiconductor substrate has the first conductivity.
9. The semiconductor device of claim 8 , further comprising at least one dummy gate structure overlying the one or more highly doped wells.
10. The semiconductor device of claim 7 , further comprising a first metallization layer over the semiconductor substrate, wherein the first metallization layer comprises a conductive region that encircles the first region in a top down view.
11. The semiconductor device of claim 10 , further comprising contacts electrically connecting the conductive region with the pick-up device.
12. The semiconductor device of claim 10 , further comprising a second metallization layer between the first metallization layer and the semiconductor substrate, wherein the second metallization layer comprises a conductive line.
13. The semiconductor device of claim 12 , further comprising first vias extending from the first metallization layer through the second metallization layer.
14. The semiconductor device of claim 13 , further comprising second vias extending from the second metallization layer, wherein the first vias have a larger width than the second vias.
15. A semiconductor device comprising:
a first driving transistor with a first drain coupled to a node; and
an electrostatic discharge device coupled to the node, wherein the electrostatic discharge device comprises:
a semiconductor fin over a substrate;
a first gate stack over the semiconductor fin;
a second gate stack over the semiconductor fin; and
a drain region extending from the first gate stack to the second gate stack, wherein the drain region has a merged drain epitaxy region and a non-merged drain epitaxy region.
16. The semiconductor device of claim 15 , wherein the first driving transistor is an input driver circuit.
17. The semiconductor device of claim 15 , wherein the first driving transistor is an output driver circuit.
18. The semiconductor device of claim 15 , further comprising a second driving transistor coupled to the node.
19. The semiconductor device of claim 15 , where the electrostatic discharge device is a standalone device.
20. The semiconductor device of claim 15 , wherein the electrostatic discharge device is incorporated into a driving circuit with the first driving transistor.