Error rate meter included in a semiconductor die
An apparatus for performing an electrical test at a device is described. In one general implementation, an apparatus may include a memory, a receiver, and a processor. The receiver is configured to receive a test signal, convert the test signal into a digital test signal (bit stream) and store the digital test signal in the memory. The receiver identifies when a pre-defined number of bits of the bit stream are available in the memory. The processor is configured to perform a logic operation on the bit stream and a reference signal, generate a test result based on the logic operation, and determine whether the test result satisfies a condition. In some implementations, the processor may be configured to synchronize the digital test signal with the reference signal prior to performing of the logic operation.
1. An apparatus, comprising:
a memory configured to store a reference signal that includes a plurality of phase-shifted sequences;
an antenna configured to receive a test signal that corresponds to a repeated bit stream;
a receiver configured to store the repeated bit stream in the memory and identify when a pre-defined number of bits of the repeated bit stream are available in the memory; and
a processor configured to perform a self-test, the self-test including:
synchronizing the repeating bit stream and the reference signal based on a correlation between the repeated bit stream and each of the phase-shifted sequences;
performing a logic operation on the synchronized repeating bit stream and the reference signal sequence; and
generating a test result based on the logic operation satisfying a condition.
2. The apparatus of claim 1 , wherein the self-test is initiated without an external trigger from a source of the test signal.
3. The apparatus of claim 1 , wherein the plurality of phase shifted sequences are phase-shifted versions of a pseudorandom binary sequence (PRBS), and wherein each of the plurality of phase-shifted versions of the sequence are stored at a particular memory address in the memory.
4. The apparatus of claim 1 , wherein the logic operation includes at least one of an exclusive OR (XOR) operation, a summation operation, or a result operation.
5. The apparatus of claim 1 , wherein the processor is configured to perform the logic operation that includes an exclusive OR (XOR) operation, and wherein the XOR operation includes:
comparing each bit of the bit stream with a corresponding bit of the reference signal; and
generating, for each comparison, a high logic value when a bit of the bit stream fails to match the corresponding bit of the reference signal or a low logic value when the bit of the bit stream matches the corresponding bit of the reference signal.
6. The apparatus of claim 1 , wherein the processor is configured to perform the logic operation that includes exclusive OR (XOR) and summation operations, and
wherein the XOR operation includes:
comparing each bit of the bit stream with a corresponding bit of the reference signal;
generating, for each comparison, a high logic value when a bit of the bit stream fails to match the corresponding bit of the reference signal or a low logic value when the bit of the bit stream matches the corresponding bit of the reference signal, and
wherein the summation operation includes:
adding generated high logic values to determine a total number of bits that failed to match and adding generated low logic values to determine a total number of matched bits.
7. The apparatus of claim 1 , wherein the processor is configured to perform the logic operation that includes exclusive OR (XOR), summation, and result operations, and
wherein the XOR operation includes:
comparing each bit of the bit stream with a corresponding bit of the reference signal;
generating, for each comparison, a high logic value when a bit of the bit stream fails to match the corresponding bit of the reference signal or a low logic value when the bit of the bit stream matches the corresponding bit of the reference signal,
wherein the summation operation includes:
adding generated high logic values to determine a total number of bits that failed to match and adding low logic values to determine a total number of matched bits; and
wherein the result operation includes:
determining whether the test result satisfies the condition based on a test criterion configured at the apparatus, wherein the test criterion is based on the total number of bits that failed to match.
8. The apparatus of claim 1 ,
wherein the apparatus is a first device under test (DUT) and the test signal is transmitted wirelessly by a second DUT; and
wherein the test results include a quality of reception in an environment of the first DUT and the second DUT.
9. An apparatus, comprising:
a memory configured to store a reference signal that includes a plurality of phase-shifted sequences;
a receiver configured to:
receive a test signal that corresponds to a repeated bit stream;
store the repeated bit stream in the memory;
identify when a pre-defined number of bits of the repeated bit stream are available in the memory; and
a processor configured to:
perform, in response to the identifying, a self-test, the self-test including:
synchronizing the repeating bit stream and the reference signal based on a correlation between the repeated bit stream and each of the phase-shifted sequences;
performing a logic operation on the synchronized repeating bit stream and the reference signal sequence; and
generating a test result based on the logic operation satisfying a condition.
10. The apparatus of claim 9 , wherein the self-test is initiated without an external trigger from a source of the test signal.
11. A method, comprising:
receiving, at a device under test (DUT), a test signal that corresponds to a repeated bit stream;
storing the repeated bit stream in a receiver memory portion;
identifying, by the DUT, when a pre-defined number of bits of the repeated bit stream are available in the receiver memory portion;
performing, by the DUT, in response to the identifying, a self-test, the self-test including:
synchronizing the repeating bit stream and a reference signal including a plurality of phase-shifted sequences, the synchronizing based on a correlation between the repeated bit stream and each of the phase-shifted sequences;
performing a logic operation on the synchronized repeating bit stream and the reference signal sequence; and
generating a test result based on the logic operation satisfying a condition.
12. The method of claim 11 , wherein the self-test is initiated without an external trigger from a source of the test signal.
13. The method of claim 11 , wherein the plurality of phase shifted sequences are phase-shifted versions of a pseudorandom binary sequence (PRBS), and wherein each of the plurality of phase-shifted versions of the sequence are stored at a particular memory address in the memory.
14. The method of claim 11 , wherein the logic operation includes at least one of an exclusive OR (XOR) operation, a summation operation, or a result operation.
15. The method of claim 11 , wherein the logic operation includes performing an exclusive OR (XOR) operation, and wherein the XOR operation includes:
comparing each bit of the bit stream with a corresponding bit of the reference signal; and
generating, for each comparison, a high logic value when a bit of the bit stream fails to match the corresponding bit of the reference signal or a low logic value when the bit of the bit stream matches the corresponding bit of the reference signal.
16. The method of claim 11 , wherein the logic operation includes performing exclusive OR (XOR) and summation operations,
wherein the XOR operation includes:
comparing each bit of the bit stream with a corresponding bit of the reference signal;
generating, for each comparison, a high logic value when a bit of the bit stream fails to match the corresponding bit of the reference signal or a low logic value when the bit of the bit stream matches the corresponding bit of the reference signal, and
wherein the summation operation includes:
adding generated high logic values to determine a total number of bits that failed to match and adding generated low logic values to determine a total number of matched bits.
17. The method of claim 11 , wherein the logic operation includes performing exclusive OR (XOR), summation, and result operations, comprising:
wherein the XOR operation includes:
comparing each bit of the bit stream with a corresponding bit of the reference signal;
generating, for each comparison, a high logic value when a bit of the bit stream fails to match the corresponding bit of the reference signal or a low logic value when the bit of the bit stream matches the corresponding bit of the reference signal,
wherein the summation operation includes:
adding generated high logic values to determine a total number of bits that failed to match and adding generated low logic values to determine a total number of matched bits; and
wherein the result operation includes:
determining whether the test result satisfies the condition based on a test criterion configured at the DUT, wherein the test criterion is based on the total number of bits that failed to match.