IP Library Granted Patent US 10,609,005
Granted Patent B2
US 10,609,005 · App. 15/897,867 · Granted Mar 31, 2020

Security network controller

Inventors: Kenichi Iizuka (Kanagawa, JP); Kumiko Toshimori (Kanagawa, JP); Machiko Mikami (Kanagawa, JP)
Assignee: Cypress Semiconductor Corporation
H04L63/0471G06F13/24G06F13/28G06F13/385G06F13/4063G06F21/602G06F21/72H04L9/0643
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Quick Facts
Patent No.
US 10,609,005
App. No.
15/897,867
Granted
Mar 31, 2020
Kind
B2
Abstract

A method includes using a direct memory access controller, transferring first data from a memory to an input/output control circuit via a first bus and transferring the first data from the input/output control circuit to an authentication processing circuit via a second bus, without using the first bus. The method includes using the authentication processing circuit, generating authentication data based on the first data and transferring the first data from the input/output control circuit to a cryptography processing circuit via a third bus, without using the first bus. Responsive to authentication of the first data by a first CPU coupled to the first bus, the method includes using the cryptography processing circuit, decrypting the first data, and using the direct memory access controller, transferring the decrypted first data from the input/output control circuit to the memory via the first bus.

Claims (34)

1. A data security device, comprising:

a data input/output control circuit configured to couple with a first central processing unit (CPU) and a memory via a first bus;

a cryptographic processing circuit coupled to the data input/output control circuit via a second bus, the second bus dedicated to data transfer between the data input/output control circuit and the cryptographic processing circuit, the cryptographic processing circuit to provide encryption and decryption processing; and

an authentication processing circuit coupled to the data input/output control circuit via a third bus, the third bus dedicated to data transfer between the data input/output control circuit and the authentication processing circuit, the authentication processing circuit configured to generate authentication data,

wherein data input/output control circuit is configured to transfer first data between the data input/output control circuit and the memory via the first bus without using the first CPU, transfer second data to and from the cryptographic processing circuit via the second bus without using the third bus, and transfer third data to and from the authentication processing circuit via the third bus without using the second bus.

2. The data security device of claim 1 , comprising a direct memory access controller coupled to the data input/output control circuit, wherein the direct memory access controller is configured to transfer the first data between the data input/output control circuit and the memory via the first bus without using the first CPU.

3. The data security device of claim 1 , wherein the first bus is an external bus to the data security device and the second and third busses are internal busses to the data security device.

4. The data security device of claim 1 , wherein the transfer of second data between the data input/output control circuit and the cryptographic processing circuit comprises transfer of encrypted first data or decrypted first data without using the first bus, wherein the input/output control circuit is configured to transfer the encrypted first data or decrypted first data to the memory.

5. The data security device of claim 4 , wherein the authentication processing circuit is configured to perform hash processing on the encrypted first data to generate hashed encrypted data.

6. The data security device of claim 5 , wherein the first CPU is configured to access the memory via the first bus to transfer the decrypted first data to a second CPU.

7. The data security device of claim 1 , wherein the transfer of third data between the data input/output control circuit and the authentication processing circuit comprises transfer of hashed encrypted data without using the first bus, wherein the input/output control circuit is configured to transfer the hashed encrypted data to the memory.

8. The data security device of claim 7 , wherein the first CPU is configured to access the memory via the first bus to authenticate the hashed encrypted data.

9. The data security device of claim 7 , wherein the first CPU is configured to access the memory via the first bus to transfer the hashed encrypted data to a computer network.

10. The data security device of claim 1 further comprising an external connection interface coupled to the first bus and coupled to a second CPU that is external to the device, wherein the external connection interface is configured to transfer the first data between the second CPU and the memory via the first bus.

11. The device of claim 1 further comprising a communication interface coupled to the first bus and coupled to an external computer network, wherein the communication interface is configured to transfer the first data between the external computer network and the memory via the first bus.

12. The device of claim 11 , wherein the external computer network includes the Internet.

13. A method of a data security device comprising:

using a direct memory access controller, transferring first data from a memory to an input/output control circuit via a first bus;

transferring the first data from the input/output control circuit to an authentication processing circuit via a second bus, without using the first bus and without using a third bus;

using the authentication processing circuit, generating authentication data based on the first data;

transferring the first data from the input/output control circuit to a cryptography processing circuit via a third bus, without using the first bus and without using the second bus;

responsive to authentication of the first data by a first central processing unit (CPU) coupled to the first bus, using the cryptography processing circuit, decrypting the first data; and

using the direct memory access controller, transferring the decrypted first data from the input/output control circuit to the memory via the first bus.

14. The method of claim 13 , further comprising using a communication interface, transferring the first data from a computer network to the memory via the first bus, wherein the computer network is external to the data security device.

15. The method of claim 13 , further comprising using an external connection interface, transferring the decrypted first data from the memory to a second CPU via the first bus, wherein the second CPU is external to the data security device.

16. The method of claim 13 further comprising using the input/output control circuit, transferring hashed encrypted first data as the generated authentication data from the authentication processing circuit to the input/output control circuit via the second bus, without using the first bus, and using the direct memory access controller to transfer the authentication data from the input/output control circuit to the memory via the first bus.

17. The method of claim 13 , further comprising:

using an external connection interface transferring the first data from a second CPU to the memory via the first bus, wherein the second CPU is external to the data security device;

using the cryptography processing circuit, encrypting the first data;

using the authentication processing circuit, performing a hash function on the encrypted first data; and

using the direct memory access controller, transferring the hashed encrypted first data from the input/output control circuit to the memory via the first bus.

18. The method of claim 17 , further comprising using a communication interface, transferring the hashed encrypted first data from the memory to a computer network via the first bus, wherein the computer network is external to the data security device.

19. The method of claim 18 , wherein transferring the hashed encrypted first data to a computer network comprises using the first CPU to packetize the hashed encrypted first data.

20. The method of claim 17 , comprising using the input/output control circuit, transferring the encrypted first data from the cryptography processing circuit to the input/output control circuit via the third bus, without using the first bus.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2021
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 058346/0597 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2021
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 058340/0045 →
RELEASE OF SECURITY INTEREST Recorded Sep 14, 2021
From: MUFG UNION BANK, N.A.,
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 057501/0144 →
SECURITY INTEREST Recorded Jul 31, 2019
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MUFG UNION BANK, N.A.
Reel/Frame 049917/0093 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2018
From: SPANSION LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 045545/0642 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2018
From: SPANSION LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 045529/0412 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2018
From: IIZUKA, KENICHI; TOSHIMORI, KUMIKO; MIKAMI, MACHIKO
To: SPANSION LLC
Reel/Frame 045106/0536 →
Continuity (5)
Continuation 15181201 · Jun 13, 2016
Continuation 14297200 · Jun 5, 2014
Continuation 12580993 · Oct 16, 2009
Division 10790176 · Mar 2, 2004
Related Publication 20180295111A1 · Oct 11, 2018
Cited By (1)
US 12,225,035